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link 명령어 기능(jal 등), flush 기능 추가(control hazard) 및 오류 수정

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Showing 15 changed files with 352 additions and 333 deletions
1 -module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg); 1 +module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg, link);
2 input[5:0] opcode; 2 input[5:0] opcode;
3 input[4:0] rt; 3 input[4:0] rt;
4 input[5:0] funct; 4 input[5:0] funct;
5 -output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, jump, jumpreg; 5 +output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, jump, jumpreg, link;
6 output reg[3:0] aluctrl; 6 output reg[3:0] aluctrl;
7 output reg[2:0] branch; 7 output reg[2:0] branch;
8 8
...@@ -18,6 +18,7 @@ always @(*) begin ...@@ -18,6 +18,7 @@ always @(*) begin
18 branch = 3'b000; 18 branch = 3'b000;
19 jump = 1'b0; 19 jump = 1'b0;
20 jumpreg = 1'b0; 20 jumpreg = 1'b0;
21 + link = 1'b0;
21 case(funct) 22 case(funct)
22 6'b100000: aluctrl = 4'b0010; // add 23 6'b100000: aluctrl = 4'b0010; // add
23 6'b100001: aluctrl = 4'b0010; // addu 24 6'b100001: aluctrl = 4'b0010; // addu
...@@ -35,18 +36,31 @@ always @(*) begin ...@@ -35,18 +36,31 @@ always @(*) begin
35 6'b010000: aluctrl = 4'b1010; // mfhi 36 6'b010000: aluctrl = 4'b1010; // mfhi
36 6'b010010: aluctrl = 4'b1011; // mflo 37 6'b010010: aluctrl = 4'b1011; // mflo
37 6'b001000: begin // jr 38 6'b001000: begin // jr
38 - // regdst = 1'bx; 39 + // regdst = 1'bz;
39 regwrite = 1'b0; 40 regwrite = 1'b0;
40 - // alusrc = 1'bx; 41 + // alusrc = 1'bz;
41 aluctrl = 4'b1111; 42 aluctrl = 4'b1111;
42 - memread = 1'b0; 43 + // memread = 1'b0;
43 - memwrite = 1'b0; 44 + // memwrite = 1'b0;
44 - // memtoreg = 1'bx; 45 + // memtoreg = 1'bz;
45 - branch = 3'b000; 46 + // branch = 3'b000;
46 jump = 1'b1; 47 jump = 1'b1;
47 jumpreg = 1'b1; 48 jumpreg = 1'b1;
49 + // link = 1'b0;
50 + end
51 + default: begin
52 + // regdst = 1'bz;
53 + regwrite = 1'b0;
54 + // alusrc = 1'bz;
55 + aluctrl = 4'b1111;
56 + // memread = 1'b0;
57 + // memwrite = 1'b0;
58 + // memtoreg = 1'bz;
59 + // branch = 3'b000;
60 + // jump = 1'b0;
61 + // jumpreg = 1'b0;
62 + // link = 1'b0;
48 end 63 end
49 - default: aluctrl = 4'b1111;
50 endcase 64 endcase
51 end 65 end
52 66
...@@ -61,6 +75,7 @@ always @(*) begin ...@@ -61,6 +75,7 @@ always @(*) begin
61 branch = 3'b000; 75 branch = 3'b000;
62 jump = 1'b0; 76 jump = 1'b0;
63 jumpreg = 1'b0; 77 jumpreg = 1'b0;
78 + link = 1'b0;
64 end 79 end
65 80
66 6'b001001: begin // addiu instruction 81 6'b001001: begin // addiu instruction
...@@ -74,6 +89,7 @@ always @(*) begin ...@@ -74,6 +89,7 @@ always @(*) begin
74 branch = 3'b000; 89 branch = 3'b000;
75 jump = 1'b0; 90 jump = 1'b0;
76 jumpreg = 1'b0; 91 jumpreg = 1'b0;
92 + link = 1'b0;
77 end 93 end
78 94
79 6'b001100: begin // andi instruction 95 6'b001100: begin // andi instruction
...@@ -87,100 +103,148 @@ always @(*) begin ...@@ -87,100 +103,148 @@ always @(*) begin
87 branch = 3'b000; 103 branch = 3'b000;
88 jump = 1'b0; 104 jump = 1'b0;
89 jumpreg = 1'b0; 105 jumpreg = 1'b0;
106 + link = 1'b0;
90 end 107 end
91 108
92 6'b000100: begin // beq instruction 109 6'b000100: begin // beq instruction
93 - // regdst = 1'bx; 110 + // regdst = 1'bz;
94 regwrite = 1'b0; 111 regwrite = 1'b0;
95 alusrc = 1'b0; 112 alusrc = 1'b0;
96 aluctrl = 4'b0110; // sub 113 aluctrl = 4'b0110; // sub
97 memread = 1'b0; 114 memread = 1'b0;
98 memwrite = 1'b0; 115 memwrite = 1'b0;
99 - // memtoreg = 1'bx; 116 + // memtoreg = 1'bz;
100 branch = 3'b001; 117 branch = 3'b001;
101 jump = 1'b0; 118 jump = 1'b0;
102 jumpreg = 1'b0; 119 jumpreg = 1'b0;
120 + link = 1'b0;
103 end 121 end
104 122
105 6'b000101: begin // bne instruction 123 6'b000101: begin // bne instruction
106 - // regdst = 1'bx; 124 + // regdst = 1'bz;
107 regwrite = 1'b0; 125 regwrite = 1'b0;
108 alusrc = 1'b0; 126 alusrc = 1'b0;
109 aluctrl = 4'b0110; // sub 127 aluctrl = 4'b0110; // sub
110 memread = 1'b0; 128 memread = 1'b0;
111 memwrite = 1'b0; 129 memwrite = 1'b0;
112 - // memtoreg = 1'bx; 130 + // memtoreg = 1'bz;
113 branch = 3'b010; 131 branch = 3'b010;
114 jump = 1'b0; 132 jump = 1'b0;
115 jumpreg = 1'b0; 133 jumpreg = 1'b0;
134 + link = 1'b0;
116 end 135 end
117 136
118 6'b000111: begin // bgtz instruction 137 6'b000111: begin // bgtz instruction
119 - // regdst = 1'bx; 138 + // regdst = 1'bz;
120 regwrite = 1'b0; 139 regwrite = 1'b0;
121 alusrc = 1'b0; 140 alusrc = 1'b0;
122 aluctrl = 4'b0110; // sub 141 aluctrl = 4'b0110; // sub
123 memread = 1'b0; 142 memread = 1'b0;
124 memwrite = 1'b0; 143 memwrite = 1'b0;
125 - // memtoreg = 1'bx; 144 + // memtoreg = 1'bz;
126 branch = 3'b011; 145 branch = 3'b011;
127 jump = 1'b0; 146 jump = 1'b0;
128 jumpreg = 1'b0; 147 jumpreg = 1'b0;
148 + link = 1'b0;
129 end 149 end
130 150
131 6'b000001: begin 151 6'b000001: begin
132 case(rt) 152 case(rt)
133 5'b00000: begin // bltz instruction 153 5'b00000: begin // bltz instruction
134 - // regdst = 1'bx; 154 + // regdst = 1'bz;
135 regwrite = 1'b0; 155 regwrite = 1'b0;
136 alusrc = 1'b0; 156 alusrc = 1'b0;
137 aluctrl = 4'b0110; // sub 157 aluctrl = 4'b0110; // sub
138 memread = 1'b0; 158 memread = 1'b0;
139 memwrite = 1'b0; 159 memwrite = 1'b0;
140 - // memtoreg = 1'bx; 160 + // memtoreg = 1'bz;
141 branch = 3'b100; 161 branch = 3'b100;
142 jump = 1'b0; 162 jump = 1'b0;
143 jumpreg = 1'b0; 163 jumpreg = 1'b0;
164 + link = 1'b0;
144 end 165 end
145 5'b00001: begin // bgez instruction 166 5'b00001: begin // bgez instruction
146 - // regdst = 1'bx; 167 + // regdst = 1'bz;
147 regwrite = 1'b0; 168 regwrite = 1'b0;
148 alusrc = 1'b0; 169 alusrc = 1'b0;
149 aluctrl = 4'b0110; // sub 170 aluctrl = 4'b0110; // sub
150 memread = 1'b0; 171 memread = 1'b0;
151 memwrite = 1'b0; 172 memwrite = 1'b0;
152 - // memtoreg = 1'bx; 173 + // memtoreg = 1'bz;
153 branch = 3'b101; 174 branch = 3'b101;
154 jump = 1'b0; 175 jump = 1'b0;
155 jumpreg = 1'b0; 176 jumpreg = 1'b0;
177 + link = 1'b0;
178 + end
179 + 5'b10000: begin // bltzal instruction
180 + // regdst = 1'bz;
181 + regwrite = 1'b1;
182 + alusrc = 1'b0;
183 + aluctrl = 4'b0110; // sub
184 + memread = 1'b0;
185 + memwrite = 1'b0;
186 + // memtoreg = 1'bz;
187 + branch = 3'b100;
188 + jump = 1'b0;
189 + jumpreg = 1'b0;
190 + link = 1'b1;
191 + end
192 + 5'b10001: begin // bgezal instruction
193 + // regdst = 1'bz;
194 + regwrite = 1'b1;
195 + alusrc = 1'b0;
196 + aluctrl = 4'b0110; // sub
197 + memread = 1'b0;
198 + memwrite = 1'b0;
199 + // memtoreg = 1'bz;
200 + branch = 3'b101;
201 + jump = 1'b0;
202 + jumpreg = 1'b0;
203 + link = 1'b1;
156 end 204 end
157 endcase 205 endcase
158 end 206 end
159 207
160 6'b000111: begin // blez instruction 208 6'b000111: begin // blez instruction
161 - // regdst = 1'bx; 209 + // regdst = 1'bz;
162 regwrite = 1'b0; 210 regwrite = 1'b0;
163 alusrc = 1'b0; 211 alusrc = 1'b0;
164 aluctrl = 4'b0110; // sub 212 aluctrl = 4'b0110; // sub
165 memread = 1'b0; 213 memread = 1'b0;
166 memwrite = 1'b0; 214 memwrite = 1'b0;
167 - // memtoreg = 1'bx; 215 + // memtoreg = 1'bz;
168 branch = 3'b110; 216 branch = 3'b110;
169 jump = 1'b0; 217 jump = 1'b0;
170 jumpreg = 1'b0; 218 jumpreg = 1'b0;
219 + link = 1'b0;
171 end 220 end
172 221
173 6'b000010: begin // jump instruction 222 6'b000010: begin // jump instruction
174 - // regdst = 1'bx; 223 + // regdst = 1'bz;
175 regwrite = 1'b0; 224 regwrite = 1'b0;
176 - // alusrc = 1'bx; 225 + // alusrc = 1'bz;
226 + aluctrl = 4'b1111;
227 + memread = 1'b0;
228 + memwrite = 1'b0;
229 + // memtoreg = 1'bz;
230 + branch = 3'b000;
231 + jump = 1'b1;
232 + jumpreg = 1'b0;
233 + link = 1'b0;
234 + end
235 +
236 + 6'b000011: begin // jal instruction
237 + // regdst = 1'bz;
238 + regwrite = 1'b1;
239 + // alusrc = 1'bz;
177 aluctrl = 4'b1111; 240 aluctrl = 4'b1111;
178 memread = 1'b0; 241 memread = 1'b0;
179 memwrite = 1'b0; 242 memwrite = 1'b0;
180 - // memtoreg = 1'bx; 243 + // memtoreg = 1'bz;
181 branch = 3'b000; 244 branch = 3'b000;
182 jump = 1'b1; 245 jump = 1'b1;
183 jumpreg = 1'b0; 246 jumpreg = 1'b0;
247 + link = 1'b1;
184 end 248 end
185 249
186 6'b100011: begin // lw instruction 250 6'b100011: begin // lw instruction
...@@ -194,6 +258,7 @@ always @(*) begin ...@@ -194,6 +258,7 @@ always @(*) begin
194 branch = 3'b000; 258 branch = 3'b000;
195 jump = 1'b0; 259 jump = 1'b0;
196 jumpreg = 1'b0; 260 jumpreg = 1'b0;
261 + link = 1'b0;
197 end 262 end
198 263
199 6'b101011: begin // sw instruction 264 6'b101011: begin // sw instruction
...@@ -203,23 +268,25 @@ always @(*) begin ...@@ -203,23 +268,25 @@ always @(*) begin
203 aluctrl = 4'b0010; // add 268 aluctrl = 4'b0010; // add
204 memread = 1'b0; 269 memread = 1'b0;
205 memwrite = 1'b1; 270 memwrite = 1'b1;
206 - // memtoreg = 1'bx; 271 + // memtoreg = 1'bz;
207 branch = 3'b000; 272 branch = 3'b000;
208 jump = 1'b0; 273 jump = 1'b0;
209 jumpreg = 1'b0; 274 jumpreg = 1'b0;
275 + link = 1'b0;
210 end 276 end
211 277
212 default: begin // unknown instruction 278 default: begin // unknown instruction
213 - // regdst = 1'bx; 279 + // regdst = 1'bz;
214 regwrite = 1'b0; 280 regwrite = 1'b0;
215 - // alusrc = 1'bx; 281 + // alusrc = 1'bz;
216 aluctrl = 4'b1111; 282 aluctrl = 4'b1111;
217 memread = 1'b0; 283 memread = 1'b0;
218 memwrite = 1'b0; 284 memwrite = 1'b0;
219 - // memtoreg = 1'bx; 285 + // memtoreg = 1'bz;
220 branch = 3'b000; 286 branch = 3'b000;
221 jump = 1'b0; 287 jump = 1'b0;
222 jumpreg = 1'b0; 288 jumpreg = 1'b0;
289 + link = 1'b0;
223 end 290 end
224 endcase 291 endcase
225 end 292 end
......
1 +// Data Hazard Handling
1 module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 2 module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite,
2 in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 3 in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num,
3 out_stallsignal); 4 out_stallsignal);
...@@ -21,3 +22,42 @@ end ...@@ -21,3 +22,42 @@ end
21 endmodule 22 endmodule
22 23
23 24
25 +// Control Hazard Handling
26 +module Flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, ex_branchsignal, pc_jump, pc_jumpreg, ex_pc_branch,
27 + out_flush_jump, out_flush_branch, out_pc);
28 +input clk;
29 +
30 +input ctrl_jump, ctrl_jumpreg, ex_branchsignal;
31 +input[2:0] ctrl_branch;
32 +input[31:0] pc_jump, pc_jumpreg, ex_pc_branch;
33 +
34 +output reg out_flush_jump, out_flush_branch;
35 +output reg[31:0] out_pc;
36 +
37 +reg isbranch;
38 +
39 +initial begin
40 + isbranch = 1'b0;
41 + out_flush_jump = 1'b0;
42 + out_flush_branch = 1'b0;
43 + out_pc = 32'h00000000;
44 +end
45 +
46 +always @(negedge clk) begin
47 + if(isbranch == 1'b1) begin
48 + if(ex_branchsignal == 1'b1) begin
49 + out_pc = ex_pc_branch;
50 + out_flush_branch = 1'b1;
51 + end
52 + isbranch = 1'b0;
53 + end else begin
54 + out_flush_branch = 1'b0;
55 +
56 + if(ctrl_jump == 1'b1) begin
57 + out_flush_jump = 1'b1;
58 + out_pc = (ctrl_jumpreg == 1'b0) ? pc_jump : pc_jumpreg;
59 + end else if(ctrl_branch != 3'b000) isbranch = 1'b1;
60 + else out_flush_jump = 1'b0;
61 + end
62 +end
63 +endmodule
......
...@@ -4,7 +4,7 @@ input[31:0] address; ...@@ -4,7 +4,7 @@ input[31:0] address;
4 output reg[31:0] instruction; 4 output reg[31:0] instruction;
5 5
6 reg[31:0] instr_mem[127:0]; 6 reg[31:0] instr_mem[127:0];
7 - 7 +/*
8 initial begin 8 initial begin
9 instr_mem[0] = 32'd0; 9 instr_mem[0] = 32'd0;
10 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 10 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
...@@ -17,17 +17,16 @@ instr_mem[7] = 32'b00100100000010010000000000000001; // addi, $0 $9 1 ...@@ -17,17 +17,16 @@ instr_mem[7] = 32'b00100100000010010000000000000001; // addi, $0 $9 1
17 instr_mem[8] = 32'b10101100000011010000000000111100; // sw, $0 $13 60 17 instr_mem[8] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
18 instr_mem[9] = 32'd0; 18 instr_mem[9] = 32'd0;
19 end 19 end
20 -/* 20 +*/
21 -initial begin
22 -out_clk = 1'b0;
23 21
22 +initial begin
24 instr_mem[0] = 32'd0; 23 instr_mem[0] = 32'd0;
25 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 24 instr_mem[1] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
26 instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255 25 instr_mem[2] = 32'b00100101000010000000000011111111; // addi, $8 $8 255
27 instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9 26 instr_mem[3] = 32'b00000001000010000100100000100000; // add, $8 $8 $9
28 instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10 27 instr_mem[4] = 32'b00000001000000000101000000100000; // add, $8 $0 $10
29 instr_mem[5] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1 28 instr_mem[5] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1
30 -instr_mem[6] = 32'd0; 29 +instr_mem[6] = 32'b00000001000000000111100000100000; // add, $8 $0 $15
31 instr_mem[7] = 32'b00000001000010010000000000011000; // mult, $8 $9 30 instr_mem[7] = 32'b00000001000010010000000000011000; // mult, $8 $9
32 instr_mem[8] = 32'd0; 31 instr_mem[8] = 32'd0;
33 instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12 32 instr_mem[9] = 32'b00000000000000000110000000010000; // mfhi, $12
...@@ -36,10 +35,10 @@ instr_mem[11] = 32'b10101100000011010000000000111100; // sw, $0 $13 60 ...@@ -36,10 +35,10 @@ instr_mem[11] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
36 instr_mem[12] = 32'd0; 35 instr_mem[12] = 32'd0;
37 instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1 36 instr_mem[13] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
38 instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60 37 instr_mem[14] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
39 -instr_mem[15] = 32'd0; 38 +instr_mem[15] = 32'b00001100000000000000000000010000; // jal, 16
40 instr_mem[16] = 32'b00000000000000000000000000001000; // jr, $0 39 instr_mem[16] = 32'b00000000000000000000000000001000; // jr, $0
41 end 40 end
42 -*/ 41 +
43 always @ (*) begin 42 always @ (*) begin
44 instruction = instr_mem[address/4]; 43 instruction = instr_mem[address/4];
45 end 44 end
......
1 -D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v 1 +D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
2 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 --- Compiling module test
4 --- Compiling module testA
5 --- Compiling module testB
6 --- Compiling module testPC
7 -
8 -Top level modules:
9 - test
10 -
11 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
12 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
13 --- Compiling module testbench
14 -
15 -Top level modules:
16 - testbench
17 -
18 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
19 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 2 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
20 -- Compiling module Adder 3 -- Compiling module Adder
21 4
...@@ -65,12 +48,14 @@ Top level modules: ...@@ -65,12 +48,14 @@ Top level modules:
65 MEM_WB 48 MEM_WB
66 PCcounter 49 PCcounter
67 50
68 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v 51 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
69 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 52 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
70 -- Compiling module Stall 53 -- Compiling module Stall
54 +-- Compiling module Flush
71 55
72 Top level modules: 56 Top level modules:
73 Stall 57 Stall
58 + Flush
74 59
75 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v 60 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
76 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 61 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
......
This diff is collapsed. Click to expand it.
...@@ -3,12 +3,13 @@ module MIPS_Pipeline; ...@@ -3,12 +3,13 @@ module MIPS_Pipeline;
3 3
4 wire clk; 4 wire clk;
5 wire stallsignal; 5 wire stallsignal;
6 -wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC; 6 +wire flush_jump, flush_branch;
7 +wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC, flush_pc;
7 8
8 wire[31:0] instr; // loaded instruction. 9 wire[31:0] instr; // loaded instruction.
9 10
10 -wire[4:0] reg_writereg1; // register number for the write data. 11 +wire[4:0] temp_writereg, reg_writereg1; // register number for the write data.
11 -wire[31:0] reg_writedata; // data that will be written in the register. 12 +wire[31:0] temp_writedata, reg_writedata; // data that will be written in the register.
12 wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. 13 wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
13 14
14 wire[31:0] alu_input2; // input data of ALU. 15 wire[31:0] alu_input2; // input data of ALU.
...@@ -17,7 +18,7 @@ wire[5:0] alu_branch; // indicator for branch operation. ...@@ -17,7 +18,7 @@ wire[5:0] alu_branch; // indicator for branch operation.
17 18
18 wire[31:0] mem_readdata; // data from the requested address. 19 wire[31:0] mem_readdata; // data from the requested address.
19 20
20 -wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal; 21 +wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
21 wire[3:0] ctrl_aluctrl; // control signals. 22 wire[3:0] ctrl_aluctrl; // control signals.
22 wire[2:0] ctrl_branch; 23 wire[2:0] ctrl_branch;
23 24
...@@ -31,75 +32,78 @@ wire[31:0] ifid_instr, ifid_PC_4; ...@@ -31,75 +32,78 @@ wire[31:0] ifid_instr, ifid_PC_4;
31 32
32 // ID_EX register outputs 33 // ID_EX register outputs
33 wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2; 34 wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
34 -wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg; 35 +wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg, idex_link;
35 wire[3:0] idex_aluctrl; 36 wire[3:0] idex_aluctrl;
36 wire[2:0] idex_branch; 37 wire[2:0] idex_branch;
37 wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump; 38 wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;
38 39
39 // EX_MEM register outputs 40 // EX_MEM register outputs
40 wire[4:0] exmem_writereg1; 41 wire[4:0] exmem_writereg1;
41 -wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump; 42 +wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link;
42 wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch; 43 wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;
43 44
44 // MEM_WB register outputs 45 // MEM_WB register outputs
45 wire[4:0] memwb_writereg1; 46 wire[4:0] memwb_writereg1;
46 -wire memwb_regwrite, memwb_memtoreg, memwb_jump; 47 +wire memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link;
47 -wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump; 48 +wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch;
48 49
49 - 50 +wire temp;
50 - 51 +assign temp = 1'b0;
51 -wire tempstall;
52 -assign tempstall = 1'b0;
53 52
54 Clock clock(clk); 53 Clock clock(clk);
55 -PCcounter pccounter(clk, stallsignal, nextPC, instr_address); 54 +PCcounter pccounter(clk, stallsignal, (flush_jump|flush_branch), flush_pc, instr_address);
56 -Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, 55 +Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, stallsignal);
57 - ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, 56 +Flush flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, branch_signal, {ifid_PC_4[31:28], shiftJump_output[27:0]}, reg_readdata1, addPCbranch,
58 - stallsignal); 57 + flush_jump, flush_branch, flush_pc);
59 58
60 // Instruction Fetch 59 // Instruction Fetch
61 InstructionMemory instrmem(instr_address, instr); 60 InstructionMemory instrmem(instr_address, instr);
62 Adder add_pc4(instr_address, 32'h00000004, addPC4); 61 Adder add_pc4(instr_address, 32'h00000004, addPC4);
63 62
64 -IF_ID ifid(clk, stallsignal, instr, addPC4, 63 +IF_ID ifid(clk, stallsignal,
64 + (flush_jump|flush_branch), instr, addPC4,
65 ifid_instr, ifid_PC_4); 65 ifid_instr, ifid_PC_4);
66 66
67 // Instruction Decode 67 // Instruction Decode
68 -Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg); 68 +Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0],
69 -Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11], ctrl_regdst, reg_writereg1); 69 + ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);
70 +Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11], ctrl_regdst, temp_writereg);
71 +Mux5bit mux_link_reg(temp_writereg, 5'b11111, ctrl_link, reg_writereg1);
70 Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata, memwb_regwrite, reg_readdata1, reg_readdata2); 72 Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata, memwb_regwrite, reg_readdata1, reg_readdata2);
71 SignExtend extend(ifid_instr[15:0], extend_output); 73 SignExtend extend(ifid_instr[15:0], extend_output);
72 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output); 74 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
73 75
74 -ID_EX idex(clk, stallsignal, reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 76 +ID_EX idex(clk, stallsignal, flush_branch,
77 + reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link,
75 reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, 78 reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output,
76 - idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 79 + idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link,
77 idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump); 80 idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);
78 81
79 // Execute 82 // Execute
80 Mux32bit mux_alusrc(idex_readdata2, idex_extenddata, idex_alusrc, alu_input2); 83 Mux32bit mux_alusrc(idex_readdata2, idex_extenddata, idex_alusrc, alu_input2);
81 ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch); 84 ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch);
82 ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output); 85 ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
83 -Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch); 86 +Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch);
84 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal); 87 MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal);
85 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump); 88 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump);
86 89
87 -EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, 90 +EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link,
88 alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 91 alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch,
89 - exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, 92 + exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link,
90 exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch); 93 exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
91 94
92 // Memory 95 // Memory
93 DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exmem_memwrite, mem_readdata); 96 DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exmem_memwrite, mem_readdata);
94 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch); 97 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch);
95 98
96 -MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, 99 +MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, exmem_link,
97 - exmem_aluresult, mem_readdata, exmem_PCjump, tempPC_branch, 100 + exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, tempPC_branch,
98 - memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, 101 + memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link,
99 - memwb_aluresult, memwb_memreaddata, memwb_PCjump, memwb_PCbranch); 102 + memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch);
100 103
101 // Writeback 104 // Writeback
102 -Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, reg_writedata); 105 +Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, temp_writedata);
106 +Mux32bit mux_link_data(temp_writedata, memwb_PC_4, memwb_link, reg_writedata);
103 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC); 107 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC);
104 108
105 109
......
...@@ -7,8 +7,8 @@ wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC; ...@@ -7,8 +7,8 @@ wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
7 7
8 wire[31:0] instr; // loaded instruction. 8 wire[31:0] instr; // loaded instruction.
9 9
10 -wire[4:0] reg_writereg1; // register number for the write data. 10 +wire[4:0] temp_writereg, reg_writereg1; // register number for the write data.
11 -wire[31:0] reg_writedata; // data that will be written in the register. 11 +wire[31:0] temp_writedata, reg_writedata; // data that will be written in the register.
12 wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. 12 wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
13 13
14 wire[31:0] alu_input2; // input data of ALU. 14 wire[31:0] alu_input2; // input data of ALU.
...@@ -17,7 +17,7 @@ wire[5:0] alu_branch; // indicator for branch operation. ...@@ -17,7 +17,7 @@ wire[5:0] alu_branch; // indicator for branch operation.
17 17
18 wire[31:0] mem_readdata; // data from the requested address. 18 wire[31:0] mem_readdata; // data from the requested address.
19 19
20 -wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal; 20 +wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
21 wire[3:0] ctrl_aluctrl; 21 wire[3:0] ctrl_aluctrl;
22 wire[2:0] ctrl_branch; // control signals. 22 wire[2:0] ctrl_branch; // control signals.
23 23
...@@ -32,12 +32,14 @@ InstructionMemory instrmem(instr_address, instr); ...@@ -32,12 +32,14 @@ InstructionMemory instrmem(instr_address, instr);
32 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2); 32 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
33 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch); 33 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
34 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata); 34 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
35 -Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg); 35 +Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);
36 36
37 -Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1); 37 +Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, temp_writereg);
38 +Mux5bit mux_link_reg(temp_writereg, 5'b11111, ctrl_link, reg_writereg1);
38 MuxBranchSignal mux_branchsignal(alu_branch, ctrl_branch, branch_signal); 39 MuxBranchSignal mux_branchsignal(alu_branch, ctrl_branch, branch_signal);
39 Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2); 40 Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
40 -Mux32bit mux_memtoreg(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata); 41 +Mux32bit mux_memtoreg(alu_result, mem_readdata, ctrl_memtoreg, temp_writedata);
42 +Mux32bit mux_link_data(temp_writedata, addPC4, ctrl_link, reg_writedata);
41 Mux32bit mux_branch(addPC4, addPCbranch, branch_signal , tempPC_branch); 43 Mux32bit mux_branch(addPC4, addPCbranch, branch_signal , tempPC_branch);
42 Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump); 44 Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
43 Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC); 45 Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
......
1 -module IF_ID(clk, stall, in_instruction, in_PC_4, 1 +module IF_ID(clk, stall, flush, in_instruction, in_PC_4,
2 out_instruction, out_PC_4); 2 out_instruction, out_PC_4);
3 -input clk, stall; 3 +input clk, stall, flush;
4 4
5 input[31:0] in_instruction, in_PC_4; 5 input[31:0] in_instruction, in_PC_4;
6 6
...@@ -8,65 +8,72 @@ output reg[31:0] out_instruction, out_PC_4; ...@@ -8,65 +8,72 @@ output reg[31:0] out_instruction, out_PC_4;
8 8
9 reg[31:0] temp_instruction, temp_PC_4; 9 reg[31:0] temp_instruction, temp_PC_4;
10 10
11 -reg stallfinished; 11 +reg first, stallfinished, flushed;
12 12
13 initial begin 13 initial begin
14 + first = 1'b1;
14 stallfinished = 1'b0; 15 stallfinished = 1'b0;
16 + flushed = 1'b0;
15 end 17 end
16 -
17 always @(posedge clk) begin 18 always @(posedge clk) begin
18 -
19 if(stall == 1'b1) begin 19 if(stall == 1'b1) begin
20 + out_instruction <= temp_instruction;
21 + out_PC_4 <= temp_PC_4;
22 + end
23 + else if(flush == 1'b1) begin
20 out_instruction <= 32'h00000000; 24 out_instruction <= 32'h00000000;
21 out_PC_4 <= 32'h00000000; 25 out_PC_4 <= 32'h00000000;
22 end 26 end
27 + else if(flushed == 1'b1) begin
28 + out_instruction <= 32'h00000000;
29 + out_PC_4 <= 32'h00000000;
30 + stallfinished = 1'b0;
31 + flushed = 1'b0;
32 + end
23 else if(stallfinished == 1'b1) begin 33 else if(stallfinished == 1'b1) begin
24 out_instruction <= temp_instruction; 34 out_instruction <= temp_instruction;
25 out_PC_4 <= temp_PC_4; 35 out_PC_4 <= temp_PC_4;
26 -
27 stallfinished = 1'b0; 36 stallfinished = 1'b0;
37 + flushed = 1'b0;
28 end 38 end
29 else begin 39 else begin
30 out_instruction <= in_instruction; 40 out_instruction <= in_instruction;
31 out_PC_4 <= in_PC_4; 41 out_PC_4 <= in_PC_4;
32 end 42 end
33 end 43 end
34 -
35 always @(posedge stall) begin 44 always @(posedge stall) begin
36 temp_instruction <= out_instruction; 45 temp_instruction <= out_instruction;
37 temp_PC_4 <= out_PC_4; 46 temp_PC_4 <= out_PC_4;
38 end 47 end
39 -always @(negedge stall) begin 48 +always @(negedge stall) stallfinished = 1'b1;
40 - stallfinished = 1'b1; 49 +always @(negedge flush) flushed = 1'b1;
41 -end
42 endmodule 50 endmodule
43 51
44 52
45 -module ID_EX(clk, stall, in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 53 +module ID_EX(clk, stall, flush,
54 + in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, in_link,
46 in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, 55 in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump,
47 - out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 56 + out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, out_link,
48 out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump); 57 out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
49 -input clk, stall; 58 +input clk, stall, flush;
50 59
51 input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2; 60 input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
52 -input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg; 61 +input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg, in_link;
53 input[3:0] in_aluctrl; 62 input[3:0] in_aluctrl;
54 input[2:0] in_branch; 63 input[2:0] in_branch;
55 input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump; 64 input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump;
56 65
57 output reg[4:0] out_writereg_num, out_readreg_num1, out_readreg_num2; 66 output reg[4:0] out_writereg_num, out_readreg_num1, out_readreg_num2;
58 -output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg; 67 +output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg, out_link;
59 output reg[3:0] out_aluctrl; 68 output reg[3:0] out_aluctrl;
60 output reg[2:0] out_branch; 69 output reg[2:0] out_branch;
61 output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump; 70 output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;
62 71
63 reg stallfinished; 72 reg stallfinished;
64 73
65 -initial begin 74 +initial stallfinished = 1'b0;
66 - stallfinished = 1'b0;
67 -end
68 always @(posedge clk) begin 75 always @(posedge clk) begin
69 - if(stall == 1'b1) begin 76 + if(stall == 1'b1 || flush == 1'b1) begin
70 out_writereg_num <= 5'b00000; 77 out_writereg_num <= 5'b00000;
71 out_readreg_num1 <= 5'b00000; 78 out_readreg_num1 <= 5'b00000;
72 out_readreg_num2 <= 5'b00000; 79 out_readreg_num2 <= 5'b00000;
...@@ -80,6 +87,7 @@ always @(posedge clk) begin ...@@ -80,6 +87,7 @@ always @(posedge clk) begin
80 out_branch <= 3'b000; 87 out_branch <= 3'b000;
81 out_jump <= 1'b0; 88 out_jump <= 1'b0;
82 out_jumpreg <= 1'b0; 89 out_jumpreg <= 1'b0;
90 + out_link <= 1'b0;
83 91
84 out_readdata1 <= 32'h00000000; 92 out_readdata1 <= 32'h00000000;
85 out_readdata2 <= 32'h00000000; 93 out_readdata2 <= 32'h00000000;
...@@ -101,6 +109,7 @@ always @(posedge clk) begin ...@@ -101,6 +109,7 @@ always @(posedge clk) begin
101 out_branch <= 3'b000; 109 out_branch <= 3'b000;
102 out_jump <= 1'b0; 110 out_jump <= 1'b0;
103 out_jumpreg <= 1'b0; 111 out_jumpreg <= 1'b0;
112 + out_link <= 1'b0;
104 113
105 out_readdata1 <= 32'h00000000; 114 out_readdata1 <= 32'h00000000;
106 out_readdata2 <= 32'h00000000; 115 out_readdata2 <= 32'h00000000;
...@@ -124,6 +133,7 @@ always @(posedge clk) begin ...@@ -124,6 +133,7 @@ always @(posedge clk) begin
124 out_branch <= in_branch; 133 out_branch <= in_branch;
125 out_jump <= in_jump; 134 out_jump <= in_jump;
126 out_jumpreg <= in_jumpreg; 135 out_jumpreg <= in_jumpreg;
136 + out_link <= in_link;
127 137
128 out_readdata1 <= in_readdata1; 138 out_readdata1 <= in_readdata1;
129 out_readdata2 <= in_readdata2; 139 out_readdata2 <= in_readdata2;
...@@ -132,24 +142,21 @@ always @(posedge clk) begin ...@@ -132,24 +142,21 @@ always @(posedge clk) begin
132 out_tempPCjump <= in_tempPCjump; 142 out_tempPCjump <= in_tempPCjump;
133 end 143 end
134 end 144 end
135 -always @(negedge stall) begin 145 +always @(negedge stall or negedge flush) stallfinished = 1'b1;
136 - stallfinished = 1'b1;
137 -end
138 -
139 endmodule 146 endmodule
140 147
141 148
142 -module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, 149 +module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link,
143 in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch, 150 in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch,
144 - out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 151 + out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_link,
145 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch); 152 out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
146 input clk; 153 input clk;
147 154
148 input[4:0] in_writereg_num; 155 input[4:0] in_writereg_num;
149 -input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump; 156 +input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link;
150 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch; 157 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
151 output reg[4:0] out_writereg_num; 158 output reg[4:0] out_writereg_num;
152 -output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump; 159 +output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_link;
153 output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch; 160 output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;
154 161
155 always @(posedge clk) begin 162 always @(posedge clk) begin
...@@ -160,6 +167,7 @@ always @(posedge clk) begin ...@@ -160,6 +167,7 @@ always @(posedge clk) begin
160 out_memtoreg <= in_memtoreg; 167 out_memtoreg <= in_memtoreg;
161 out_branch <= in_branch; 168 out_branch <= in_branch;
162 out_jump <= in_jump; 169 out_jump <= in_jump;
170 + out_link <= in_link;
163 171
164 out_aluresult <= in_aluresult; 172 out_aluresult <= in_aluresult;
165 out_mem_writedata <= in_mem_writedata; 173 out_mem_writedata <= in_mem_writedata;
...@@ -170,33 +178,35 @@ end ...@@ -170,33 +178,35 @@ end
170 endmodule 178 endmodule
171 179
172 180
173 -module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 181 +module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_link, in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch,
174 - out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCjump, out_PCbranch); 182 + out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_link, out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch);
175 input clk; 183 input clk;
176 184
177 input[4:0] in_writereg_num; 185 input[4:0] in_writereg_num;
178 -input in_regwrite, in_memtoreg, in_jump; 186 +input in_regwrite, in_memtoreg, in_jump, in_link;
179 -input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump; 187 +input[31:0] in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch;
180 output reg[4:0] out_writereg_num; 188 output reg[4:0] out_writereg_num;
181 -output reg out_regwrite, out_memtoreg, out_jump; 189 +output reg out_regwrite, out_memtoreg, out_jump, out_link;
182 -output reg[31:0] out_aluresult, out_memreaddata, out_PCbranch, out_PCjump; 190 +output reg[31:0] out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch;
183 191
184 always @(posedge clk) begin 192 always @(posedge clk) begin
185 out_writereg_num <= in_writereg_num; 193 out_writereg_num <= in_writereg_num;
186 out_regwrite <= in_regwrite; 194 out_regwrite <= in_regwrite;
187 out_memtoreg <= in_memtoreg; 195 out_memtoreg <= in_memtoreg;
188 out_jump <= in_jump; 196 out_jump <= in_jump;
197 + out_link <= in_link;
189 198
190 out_aluresult <= in_aluresult; 199 out_aluresult <= in_aluresult;
191 out_memreaddata <= in_memreaddata; 200 out_memreaddata <= in_memreaddata;
201 + out_PC_4 <= in_PC_4;
192 out_PCjump <= in_PCjump; 202 out_PCjump <= in_PCjump;
193 out_PCbranch <= in_PCbranch; 203 out_PCbranch <= in_PCbranch;
194 end 204 end
195 endmodule 205 endmodule
196 206
197 /* Not Finished */ 207 /* Not Finished */
198 -module PCcounter(clk, stall, in_pc, out_nextpc); 208 +module PCcounter(clk, stall, flush, in_pc, out_nextpc);
199 -input clk, stall; 209 +input clk, stall, flush;
200 210
201 input[31:0] in_pc; 211 input[31:0] in_pc;
202 output reg[31:0] out_nextpc; 212 output reg[31:0] out_nextpc;
...@@ -210,12 +220,10 @@ initial begin ...@@ -210,12 +220,10 @@ initial begin
210 end 220 end
211 221
212 always @(posedge clk) begin 222 always @(posedge clk) begin
213 -
214 if(stallfinished == 1'b1) stallfinished = 1'b0; 223 if(stallfinished == 1'b1) stallfinished = 1'b0;
215 - else if(stall == 1'b0) PC = PC+4; 224 + else if(stall == 1'b0 && flush == 1'b0) PC = PC+4;
216 out_nextpc = PC; 225 out_nextpc = PC;
217 end 226 end
218 -always @(negedge stall) begin 227 +always @(negedge stall or negedge flush) stallfinished = 1'b1;
219 - stallfinished = 1'b1; 228 +always @(posedge flush) PC = in_pc;
220 -end
221 endmodule 229 endmodule
......
No preview for this file type
...@@ -9,7 +9,7 @@ z2 ...@@ -9,7 +9,7 @@ z2
9 cModel Technology 9 cModel Technology
10 dC:/Modeltech_pe_edu_10.4a/examples 10 dC:/Modeltech_pe_edu_10.4a/examples
11 vAdder 11 vAdder
12 -Z0 !s110 1591621209 12 +Z0 !s110 1591983139
13 !i10b 1 13 !i10b 1
14 !s100 LKl?GBS:oo[A[hLP0Qb^_1 14 !s100 LKl?GBS:oo[A[hLP0Qb^_1
15 IlbJEP?2C3Ya>zhzD12^S]1 15 IlbJEP?2C3Ya>zhzD12^S]1
...@@ -23,7 +23,7 @@ Z3 OP;L;10.4a;61 ...@@ -23,7 +23,7 @@ Z3 OP;L;10.4a;61
23 r1 23 r1
24 !s85 0 24 !s85 0
25 31 25 31
26 -Z4 !s108 1591621208.000000 26 +Z4 !s108 1591983139.000000
27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 27 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v| 28 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
29 !s101 -O0 29 !s101 -O0
...@@ -45,7 +45,7 @@ R3 ...@@ -45,7 +45,7 @@ R3
45 r1 45 r1
46 !s85 0 46 !s85 0
47 31 47 31
48 -Z6 !s108 1591621209.000000 48 +R4
49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 49 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v| 50 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
51 !s101 -O0 51 !s101 -O0
...@@ -67,7 +67,7 @@ R3 ...@@ -67,7 +67,7 @@ R3
67 r1 67 r1
68 !s85 0 68 !s85 0
69 31 69 31
70 -R6 70 +R4
71 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v| 71 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
72 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v| 72 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
73 !s101 -O0 73 !s101 -O0
...@@ -75,13 +75,13 @@ R6 ...@@ -75,13 +75,13 @@ R6
75 R5 75 R5
76 n@clock 76 n@clock
77 vControl 77 vControl
78 -R0 78 +Z6 !s110 1591983140
79 !i10b 1 79 !i10b 1
80 -!s100 4N9S2_;3jCoh7S5CM:UBB2 80 +!s100 NdQKEjPCPSHG<0<4CTgfz1
81 -IiJiDhRWdHkEd649hCz4P;1 81 +Io?;>IIVLB=Zl;M_TSQZ9I2
82 R1 82 R1
83 R2 83 R2
84 -w1591452194 84 +w1591975942
85 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 85 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
86 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v 86 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
87 L0 1 87 L0 1
...@@ -89,7 +89,7 @@ R3 ...@@ -89,7 +89,7 @@ R3
89 r1 89 r1
90 !s85 0 90 !s85 0
91 31 91 31
92 -R6 92 +R4
93 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v| 93 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
94 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v| 94 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
95 !s101 -O0 95 !s101 -O0
...@@ -97,7 +97,7 @@ R6 ...@@ -97,7 +97,7 @@ R6
97 R5 97 R5
98 n@control 98 n@control
99 vDataMemory 99 vDataMemory
100 -R0 100 +R6
101 !i10b 1 101 !i10b 1
102 !s100 e=5E[GS05J<RCdT=KSMX_1 102 !s100 e=5E[GS05J<RCdT=KSMX_1
103 I9=L>R4ccfGY8^T;U50LY?1 103 I9=L>R4ccfGY8^T;U50LY?1
...@@ -111,7 +111,7 @@ R3 ...@@ -111,7 +111,7 @@ R3
111 r1 111 r1
112 !s85 0 112 !s85 0
113 31 113 31
114 -R6 114 +Z7 !s108 1591983140.000000
115 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v| 115 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v| 116 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
117 !s101 -O0 117 !s101 -O0
...@@ -119,79 +119,101 @@ R6 ...@@ -119,79 +119,101 @@ R6
119 R5 119 R5
120 n@data@memory 120 n@data@memory
121 vEX_MEM 121 vEX_MEM
122 -Z7 !s110 1591621210 122 +Z8 !s110 1591983141
123 !i10b 1 123 !i10b 1
124 -!s100 7M;f[J6l]Q8I7]G9EaW4b2 124 +!s100 ^^:n;T<R5`c:oReRzT=QT3
125 -I4[]:7KKT=g2:;MLnikc863 125 +IUKd^A=OJc08kD[zWg_`SA2
126 R1 126 R1
127 R2 127 R2
128 -Z8 w1591621089 128 +Z9 w1591982553
129 -Z9 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 129 +Z10 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
130 -Z10 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v 130 +Z11 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
131 -L0 142 131 +L0 149
132 R3 132 R3
133 r1 133 r1
134 !s85 0 134 !s85 0
135 31 135 31
136 -Z11 !s108 1591621210.000000 136 +Z12 !s108 1591983141.000000
137 -Z12 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 137 +Z13 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
138 -Z13 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v| 138 +Z14 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
139 !s101 -O0 139 !s101 -O0
140 !i113 1 140 !i113 1
141 R5 141 R5
142 n@e@x_@m@e@m 142 n@e@x_@m@e@m
143 -vID_EX 143 +vFlush
144 -R7 144 +R6
145 !i10b 1 145 !i10b 1
146 -!s100 id94:21DzMBedgX<6MLIW3 146 +!s100 G^dZ>]FGe3h^`=G1P?aLA1
147 -ILTL53m=Ci^KdWXiJ:6G`E2 147 +IaJUhT0Va;e^W1QK:FQaQi2
148 R1 148 R1
149 R2 149 R2
150 +Z15 w1591970913
151 +Z16 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
152 +Z17 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
153 +L0 26
154 +R3
155 +r1
156 +!s85 0
157 +31
158 +R7
159 +Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
160 +Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
161 +!s101 -O0
162 +!i113 1
163 +R5
164 +n@flush
165 +vID_EX
150 R8 166 R8
167 +!i10b 1
168 +!s100 ?MgFelQ<oVo:WHdjbIKo00
169 +ITSSi3aWmi:I7boRWd[i>H3
170 +R1
171 +R2
151 R9 172 R9
152 R10 173 R10
153 -L0 45 174 +R11
175 +L0 53
154 R3 176 R3
155 r1 177 r1
156 !s85 0 178 !s85 0
157 31 179 31
158 -R11
159 R12 180 R12
160 R13 181 R13
182 +R14
161 !s101 -O0 183 !s101 -O0
162 !i113 1 184 !i113 1
163 R5 185 R5
164 n@i@d_@e@x 186 n@i@d_@e@x
165 vIF_ID 187 vIF_ID
166 -R7 188 +R8
167 !i10b 1 189 !i10b 1
168 -!s100 ?M?9X@=b^flc3blH:Dn^g2 190 +!s100 bEXSIWd8gnI`]GAUe_N>70
169 -I^7T81LjBP2[g8ie`ATZ=G2 191 +IRmIoA42QB9iZ_NYh`X79>3
170 R1 192 R1
171 R2 193 R2
172 -R8
173 R9 194 R9
174 R10 195 R10
196 +R11
175 L0 1 197 L0 1
176 R3 198 R3
177 r1 199 r1
178 !s85 0 200 !s85 0
179 31 201 31
180 -R11
181 R12 202 R12
182 R13 203 R13
204 +R14
183 !s101 -O0 205 !s101 -O0
184 !i113 1 206 !i113 1
185 R5 207 R5
186 n@i@f_@i@d 208 n@i@f_@i@d
187 vInstructionMemory 209 vInstructionMemory
188 -R7 210 +R6
189 !i10b 1 211 !i10b 1
190 -!s100 <VK`==0E@Llng:<adzYd80 212 +!s100 dUP:<mGld?9A^?GbR`HX41
191 -I6V??0<R5lO5JZ[eh2?Qo13 213 +Ijoe6hdS43:Kg7S<nf[6_S3
192 R1 214 R1
193 R2 215 R2
194 -w1591579676 216 +w1591979413
195 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 217 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
196 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v 218 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
197 L0 1 219 L0 1
...@@ -199,7 +221,7 @@ R3 ...@@ -199,7 +221,7 @@ R3
199 r1 221 r1
200 !s85 0 222 !s85 0
201 31 223 31
202 -R11 224 +R7
203 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 225 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
204 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v| 226 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
205 !s101 -O0 227 !s101 -O0
...@@ -207,35 +229,35 @@ R11 ...@@ -207,35 +229,35 @@ R11
207 R5 229 R5
208 n@instruction@memory 230 n@instruction@memory
209 vMEM_WB 231 vMEM_WB
210 -R7 232 +R8
211 !i10b 1 233 !i10b 1
212 -!s100 [HWKoHB:zC]dGeW[NDE]30 234 +!s100 9m=P24TTjNA?g>P@e6;[=2
213 -IEjo6PSl[2V[fN=O@DA7W_0 235 +I3VBN<k:`mX_jIkFWMoi3a2
214 R1 236 R1
215 R2 237 R2
216 -R8
217 R9 238 R9
218 R10 239 R10
219 -L0 173 240 +R11
241 +L0 181
220 R3 242 R3
221 r1 243 r1
222 !s85 0 244 !s85 0
223 31 245 31
224 -R11
225 R12 246 R12
226 R13 247 R13
248 +R14
227 !s101 -O0 249 !s101 -O0
228 !i113 1 250 !i113 1
229 R5 251 R5
230 n@m@e@m_@w@b 252 n@m@e@m_@w@b
231 vMIPS_Pipeline 253 vMIPS_Pipeline
232 -R7 254 +R6
233 !i10b 1 255 !i10b 1
234 -!s100 O:NALVmB^PBj5HkG<@2XA3 256 +!s100 AkG9Fhg`zlP55C:McA:FM2
235 -I5L3]J:Nz<PQZe=N8z]::o3 257 +IZRIYdAdZBSFN3o<CV_WgK0
236 R1 258 R1
237 R2 259 R2
238 -w1591621120 260 +w1591980998
239 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 261 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
240 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v 262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
241 L0 2 263 L0 2
...@@ -243,7 +265,7 @@ R3 ...@@ -243,7 +265,7 @@ R3
243 r1 265 r1
244 !s85 0 266 !s85 0
245 31 267 31
246 -R11 268 +R7
247 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
248 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v| 270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
249 !s101 -O0 271 !s101 -O0
...@@ -251,13 +273,13 @@ R11 ...@@ -251,13 +273,13 @@ R11
251 R5 273 R5
252 n@m@i@p@s_@pipeline 274 n@m@i@p@s_@pipeline
253 vMIPS_SingleCycle 275 vMIPS_SingleCycle
254 -R7 276 +R8
255 !i10b 1 277 !i10b 1
256 -!s100 Zz<Q962j57a4IzW0mQ=5=1 278 +!s100 ;_UzWlV_FikM_gED@zTjP2
257 -IMJcJ>deKe`cm>JGo56D8H2 279 +IQEAV;clN[65lKfZREk<=Q1
258 R1 280 R1
259 R2 281 R2
260 -w1591531598 282 +w1591976493
261 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 283 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
262 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v 284 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
263 L0 1 285 L0 1
...@@ -265,7 +287,7 @@ R3 ...@@ -265,7 +287,7 @@ R3
265 r1 287 r1
266 !s85 0 288 !s85 0
267 31 289 31
268 -R11 290 +R7
269 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 291 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
270 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v| 292 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
271 !s101 -O0 293 !s101 -O0
...@@ -273,95 +295,95 @@ R11 ...@@ -273,95 +295,95 @@ R11
273 R5 295 R5
274 n@m@i@p@s_@single@cycle 296 n@m@i@p@s_@single@cycle
275 vMux32bit 297 vMux32bit
276 -R7 298 +R8
277 !i10b 1 299 !i10b 1
278 !s100 foJG^YU75_eND1Og;6Z>O1 300 !s100 foJG^YU75_eND1Og;6Z>O1
279 II3=gjhQD0_cn8mlDL]@bi1 301 II3=gjhQD0_cn8mlDL]@bi1
280 R1 302 R1
281 R2 303 R2
282 -Z14 w1591452448 304 +Z20 w1591452448
283 -Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 305 +Z21 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
284 -Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v 306 +Z22 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
285 L0 15 307 L0 15
286 R3 308 R3
287 r1 309 r1
288 !s85 0 310 !s85 0
289 31 311 31
290 -R11 312 +R12
291 -Z17 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 313 +Z23 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
292 -Z18 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v| 314 +Z24 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
293 !s101 -O0 315 !s101 -O0
294 !i113 1 316 !i113 1
295 R5 317 R5
296 n@mux32bit 318 n@mux32bit
297 vMux5bit 319 vMux5bit
298 -R7 320 +R8
299 !i10b 1 321 !i10b 1
300 !s100 oSd=[kHDJb<:G7LN4]6@e3 322 !s100 oSd=[kHDJb<:G7LN4]6@e3
301 IfiVXg_aB2GQG7?F@=HcEi0 323 IfiVXg_aB2GQG7?F@=HcEi0
302 R1 324 R1
303 R2 325 R2
304 -R14 326 +R20
305 -R15 327 +R21
306 -R16 328 +R22
307 L0 1 329 L0 1
308 R3 330 R3
309 r1 331 r1
310 !s85 0 332 !s85 0
311 31 333 31
312 -R11 334 +R12
313 -R17 335 +R23
314 -R18 336 +R24
315 !s101 -O0 337 !s101 -O0
316 !i113 1 338 !i113 1
317 R5 339 R5
318 n@mux5bit 340 n@mux5bit
319 vMuxBranchSignal 341 vMuxBranchSignal
320 -R7 342 +R8
321 !i10b 1 343 !i10b 1
322 !s100 H1RKS9h`Y6QFX88CRc<g[0 344 !s100 H1RKS9h`Y6QFX88CRc<g[0
323 IGJT?gXMKEEWH?G^lPN79V2 345 IGJT?gXMKEEWH?G^lPN79V2
324 R1 346 R1
325 R2 347 R2
326 -R14 348 +R20
327 -R15 349 +R21
328 -R16 350 +R22
329 L0 29 351 L0 29
330 R3 352 R3
331 r1 353 r1
332 !s85 0 354 !s85 0
333 31 355 31
334 -R11 356 +R12
335 -R17 357 +R23
336 -R18 358 +R24
337 !s101 -O0 359 !s101 -O0
338 !i113 1 360 !i113 1
339 R5 361 R5
340 n@mux@branch@signal 362 n@mux@branch@signal
341 vPCcounter 363 vPCcounter
342 -R7 364 +R8
343 !i10b 1 365 !i10b 1
344 -!s100 bjm68NMba>Y8oFGU?RHPK0 366 +!s100 WeKa=V6mT9ZlU8@mTC`g42
345 -IU;F]_bg19=g^Z:GGm6U:71 367 +Il_T>dO3a82KCcjIcT0_8<0
346 R1 368 R1
347 R2 369 R2
348 -R8
349 R9 370 R9
350 R10 371 R10
351 -L0 198 372 +R11
373 +L0 208
352 R3 374 R3
353 r1 375 r1
354 !s85 0 376 !s85 0
355 31 377 31
356 -R11
357 R12 378 R12
358 R13 379 R13
380 +R14
359 !s101 -O0 381 !s101 -O0
360 !i113 1 382 !i113 1
361 R5 383 R5
362 n@p@ccounter 384 n@p@ccounter
363 vRegister 385 vRegister
364 -Z19 !s110 1591621211 386 +R8
365 !i10b 1 387 !i10b 1
366 !s100 bC`<7GaPg=bDaZoUR<ADa0 388 !s100 bC`<7GaPg=bDaZoUR<ADa0
367 I<aR5RJ2c1Qba>GdC]KZCd2 389 I<aR5RJ2c1Qba>GdC]KZCd2
...@@ -375,7 +397,7 @@ R3 ...@@ -375,7 +397,7 @@ R3
375 r1 397 r1
376 !s85 0 398 !s85 0
377 31 399 31
378 -Z20 !s108 1591621211.000000 400 +R12
379 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 401 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
380 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v| 402 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
381 !s101 -O0 403 !s101 -O0
...@@ -383,7 +405,7 @@ Z20 !s108 1591621211.000000 ...@@ -383,7 +405,7 @@ Z20 !s108 1591621211.000000
383 R5 405 R5
384 n@register 406 n@register
385 vShiftLeft2 407 vShiftLeft2
386 -R19 408 +R8
387 !i10b 1 409 !i10b 1
388 !s100 ]Zje9D[f?jFRnJBn`OeHc1 410 !s100 ]Zje9D[f?jFRnJBn`OeHc1
389 I]0TYJ]_7?FkOoY=2GlT5=3 411 I]0TYJ]_7?FkOoY=2GlT5=3
...@@ -397,7 +419,7 @@ R3 ...@@ -397,7 +419,7 @@ R3
397 r1 419 r1
398 !s85 0 420 !s85 0
399 31 421 31
400 -R20 422 +R12
401 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 423 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
402 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v| 424 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
403 !s101 -O0 425 !s101 -O0
...@@ -405,7 +427,7 @@ R20 ...@@ -405,7 +427,7 @@ R20
405 R5 427 R5
406 n@shift@left2 428 n@shift@left2
407 vSignExtend 429 vSignExtend
408 -R19 430 +R0
409 !i10b 1 431 !i10b 1
410 !s100 =4eXcc0im3]S=Kk@o:eh32 432 !s100 =4eXcc0im3]S=Kk@o:eh32
411 IFBiMm>fY8WE23A[Ye;CUj3 433 IFBiMm>fY8WE23A[Ye;CUj3
...@@ -419,7 +441,7 @@ R3 ...@@ -419,7 +441,7 @@ R3
419 r1 441 r1
420 !s85 0 442 !s85 0
421 31 443 31
422 -R20 444 +R4
423 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v| 445 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
424 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v| 446 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
425 !s101 -O0 447 !s101 -O0
...@@ -427,132 +449,24 @@ R20 ...@@ -427,132 +449,24 @@ R20
427 R5 449 R5
428 n@sign@extend 450 n@sign@extend
429 vStall 451 vStall
430 -R19 452 +R6
431 !i10b 1 453 !i10b 1
432 -!s100 N?ZClBzVEP54JoYb>Ao9:3 454 +!s100 z^N=>UeP;k2mNYmKnG`WR2
433 -I:YbV=h@`DImW@Qc>>HXoc3 455 +IOg[[<<GgT4k[<hhzADXMC3
434 R1 456 R1
435 R2 457 R2
436 -w1591618522 458 +R15
437 -8D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v 459 +R16
438 -FD:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v 460 +R17
439 -L0 1 461 +L0 2
440 R3 462 R3
441 r1 463 r1
442 !s85 0 464 !s85 0
443 31 465 31
444 -R20 466 +R7
445 -!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v| 467 +R18
446 -!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v| 468 +R19
447 !s101 -O0 469 !s101 -O0
448 !i113 1 470 !i113 1
449 R5 471 R5
450 n@stall 472 n@stall
451 -vtest
452 -Z21 !s110 1591621212
453 -!i10b 1
454 -!s100 KKL;hoG0Ojk_U;6H:]ViZ1
455 -Im`S61;3SN3Jlg_1AeFCP@3
456 -R1
457 -R2
458 -Z22 w1591501317
459 -Z23 8D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
460 -Z24 FD:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
461 -L0 1
462 -R3
463 -r1
464 -!s85 0
465 -31
466 -R20
467 -Z25 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
468 -Z26 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
469 -!s101 -O0
470 -!i113 1
471 -R5
472 -vtestA
473 -R21
474 -!i10b 1
475 -!s100 Pkg?M_BZm@c5Y24EY;_H^3
476 -InVhi@1kAoF`f3N_KB]^7i3
477 -R1
478 -R2
479 -R22
480 -R23
481 -R24
482 -L0 24
483 -R3
484 -r1
485 -!s85 0
486 -31
487 -R20
488 -R25
489 -R26
490 -!s101 -O0
491 -!i113 1
492 -R5
493 -ntest@a
494 -vtestB
495 -R21
496 -!i10b 1
497 -!s100 S@=1_l7e?W`b88GB`bZQS0
498 -Il?;09cMF7Oe7LY1h4do2M3
499 -R1
500 -R2
501 -R22
502 -R23
503 -R24
504 -L0 55
505 -R3
506 -r1
507 -!s85 0
508 -31
509 -R20
510 -R25
511 -R26
512 -!s101 -O0
513 -!i113 1
514 -R5
515 -ntest@b
516 -vtestbench
517 -!s110 1591621208
518 -!i10b 1
519 -!s100 OS>9h:91ecFHGVTRNVN]_2
520 -IR?_j2LXMem;jJUiXH@MhI0
521 -R1
522 -R2
523 -w1590428983
524 -8D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
525 -FD:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
526 -L0 1
527 -R3
528 -r1
529 -!s85 0
530 -31
531 -R4
532 -!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
533 -!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
534 -!s101 -O0
535 -!i113 1
536 -R5
537 -vtestPC
538 -R21
539 -!i10b 1
540 -!s100 L_L<o7@FSVAPYd[5blZAI1
541 -I8O06UXYD2fBn2meXg:jBC3
542 -R1
543 -R2
544 -R22
545 -R23
546 -R24
547 -L0 79
548 -R3
549 -r1
550 -!s85 0
551 -31
552 -R20
553 -R25
554 -R26
555 -!s101 -O0
556 -!i113 1
557 -R5
558 -ntest@p@c
......
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