link 명령어 기능(jal 등), flush 기능 추가(control hazard) 및 오류 수정

-module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
+module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg, link);
 input[5:0] opcode;
 input[4:0] rt;
 input[5:0] funct;
-output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, jump,  jumpreg;
+output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, jump, jumpreg, link;
 output reg[3:0] aluctrl;
 output reg[2:0] branch;
 
@@ -18,6 +18,7 @@ always @(*) begin
 			branch = 3'b000;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 			case(funct)
 				6'b100000: aluctrl = 4'b0010;	//  add
 				6'b100001: aluctrl = 4'b0010;	//  addu
@@ -35,18 +36,31 @@ always @(*) begin
 				6'b010000: aluctrl = 4'b1010;	//  mfhi
 				6'b010010: aluctrl = 4'b1011;	//  mflo
 				6'b001000: begin		//  jr
-				//	regdst = 1'bx;
+			//		regdst = 1'bz;
 					regwrite = 1'b0;
-				//	alusrc = 1'bx;
+			//		alusrc = 1'bz;
 					aluctrl = 4'b1111;
-					memread = 1'b0;
-					memwrite = 1'b0;
-				//	memtoreg = 1'bx;
-					branch = 3'b000;
+				//	memread = 1'b0;
+				//	memwrite = 1'b0;
+			//		memtoreg = 1'bz;
+				//	branch = 3'b000;
 					jump = 1'b1;
 					jumpreg = 1'b1;
+				//	link = 1'b0;
+				end
+				default: begin
+			//		regdst = 1'bz;
+					regwrite = 1'b0;
+			//		alusrc = 1'bz;
+					aluctrl = 4'b1111;
+				//	memread = 1'b0;
+				//	memwrite = 1'b0;
+			//		memtoreg = 1'bz;
+				//	branch = 3'b000;
+				//	jump = 1'b0;
+				//	jumpreg = 1'b0;
+				//	link = 1'b0;
 				end
-				default: aluctrl = 4'b1111;
 			endcase
 		end
 
@@ -61,6 +75,7 @@ always @(*) begin
 			branch = 3'b000;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b001001: begin		// addiu instruction
@@ -74,6 +89,7 @@ always @(*) begin
 			branch = 3'b000;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b001100: begin		// andi instruction
@@ -87,100 +103,148 @@ always @(*) begin
 			branch = 3'b000;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b000100: begin		// beq instruction
-		//	regdst = 1'bx;
+		//	regdst = 1'bz;
 			regwrite = 1'b0;
 			alusrc = 1'b0;
 			aluctrl = 4'b0110;		// sub
 			memread = 1'b0;
 			memwrite = 1'b0;
-		//	memtoreg = 1'bx;
+		//	memtoreg = 1'bz;
 			branch = 3'b001;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b000101: begin		// bne instruction
-		//	regdst = 1'bx;
+		//	regdst = 1'bz;
 			regwrite = 1'b0;
 			alusrc = 1'b0;
 			aluctrl = 4'b0110;		// sub
 			memread = 1'b0;
 			memwrite = 1'b0;
-		//	memtoreg = 1'bx;
+		//	memtoreg = 1'bz;
 			branch = 3'b010;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b000111: begin		// bgtz instruction
-		//	regdst = 1'bx;
+		//	regdst = 1'bz;
 			regwrite = 1'b0;
 			alusrc = 1'b0;
 			aluctrl = 4'b0110;		// sub
 			memread = 1'b0;
 			memwrite = 1'b0;
-		//	memtoreg = 1'bx;
+		//	memtoreg = 1'bz;
 			branch = 3'b011;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b000001: begin
 			case(rt)
 			5'b00000: begin		// bltz instruction
-		//		regdst = 1'bx;
+		//		regdst = 1'bz;
 				regwrite = 1'b0;
 				alusrc = 1'b0;
 				aluctrl = 4'b0110;	// sub
 				memread = 1'b0;
 				memwrite = 1'b0;
-		//		memtoreg = 1'bx;
+		//		memtoreg = 1'bz;
 				branch = 3'b100;
 				jump = 1'b0;
 				jumpreg = 1'b0;
+				link = 1'b0;
 			end
 			5'b00001: begin		// bgez instruction
-		//		regdst = 1'bx;
+		//		regdst = 1'bz;
 				regwrite = 1'b0;
 				alusrc = 1'b0;
 				aluctrl = 4'b0110;	// sub
 				memread = 1'b0;
 				memwrite = 1'b0;
-		//		memtoreg = 1'bx;
+		//		memtoreg = 1'bz;
 				branch = 3'b101;
 				jump = 1'b0;
 				jumpreg = 1'b0;
+				link = 1'b0;
+			end
+			5'b10000: begin		// bltzal instruction
+		//		regdst = 1'bz;
+				regwrite = 1'b1;
+				alusrc = 1'b0;
+				aluctrl = 4'b0110;	// sub
+				memread = 1'b0;
+				memwrite = 1'b0;
+		//		memtoreg = 1'bz;
+				branch = 3'b100;
+				jump = 1'b0;
+				jumpreg = 1'b0;
+				link = 1'b1;
+			end
+			5'b10001: begin		// bgezal instruction
+		//		regdst = 1'bz;
+				regwrite = 1'b1;
+				alusrc = 1'b0;
+				aluctrl = 4'b0110;	// sub
+				memread = 1'b0;
+				memwrite = 1'b0;
+		//		memtoreg = 1'bz;
+				branch = 3'b101;
+				jump = 1'b0;
+				jumpreg = 1'b0;
+				link = 1'b1;
 			end
 			endcase
 		end
 		
 		6'b000111: begin		// blez instruction
-		//	regdst = 1'bx;
+		//	regdst = 1'bz;
 			regwrite = 1'b0;
 			alusrc = 1'b0;
 			aluctrl = 4'b0110;		// sub
 			memread = 1'b0;
 			memwrite = 1'b0;
-		//	memtoreg = 1'bx;
+		//	memtoreg = 1'bz;
 			branch = 3'b110;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b000010: begin		// jump instruction
-		//	regdst = 1'bx;
+		//	regdst = 1'bz;
 			regwrite = 1'b0;
-		//	alusrc = 1'bx;
+		//	alusrc = 1'bz;
+			aluctrl = 4'b1111;
+			memread = 1'b0;
+			memwrite = 1'b0;
+		//	memtoreg = 1'bz;
+			branch = 3'b000;
+			jump = 1'b1;
+			jumpreg = 1'b0;
+			link = 1'b0;
+		end
+
+		6'b000011: begin		// jal instruction
+		//	regdst = 1'bz;
+			regwrite = 1'b1;
+		//	alusrc = 1'bz;
 			aluctrl = 4'b1111;
 			memread = 1'b0;
 			memwrite = 1'b0;
-		//	memtoreg = 1'bx;
+		//	memtoreg = 1'bz;
 			branch = 3'b000;
 			jump = 1'b1;
 			jumpreg = 1'b0;
+			link = 1'b1;
 		end
 
 		6'b100011: begin		// lw instruction
@@ -194,6 +258,7 @@ always @(*) begin
 			branch = 3'b000;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		6'b101011: begin		// sw instruction
@@ -203,23 +268,25 @@ always @(*) begin
 			aluctrl = 4'b0010;		// add
 			memread = 1'b0;
 			memwrite = 1'b1;
-		//	memtoreg = 1'bx;
+		//	memtoreg = 1'bz;
 			branch = 3'b000;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 
 		default: begin			// unknown instruction
-		//	regdst = 1'bx;
+		//	regdst = 1'bz;
 			regwrite = 1'b0;
-		//	alusrc = 1'bx;
+		//	alusrc = 1'bz;
 			aluctrl = 4'b1111;
 			memread = 1'b0;
 			memwrite = 1'b0;
-		//	memtoreg = 1'bx;
+		//	memtoreg = 1'bz;
 			branch = 3'b000;
 			jump = 1'b0;
 			jumpreg = 1'b0;
+			link = 1'b0;
 		end
 	endcase
 end

+// Data Hazard Handling
 module Stall(clk, in_ex_regwrite, in_mem_regwrite, in_wb_regwrite, 
 	in_readreg_num1, in_readreg_num2, in_ex_writereg_num, in_mem_writereg_num, in_wb_writereg_num, 
 	out_stallsignal);
@@ -21,3 +22,42 @@ end
 endmodule
 
 
+// Control Hazard Handling
+module Flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, ex_branchsignal, pc_jump, pc_jumpreg, ex_pc_branch, 
+	out_flush_jump, out_flush_branch, out_pc);
+input clk;
+
+input ctrl_jump, ctrl_jumpreg, ex_branchsignal;
+input[2:0] ctrl_branch;
+input[31:0] pc_jump, pc_jumpreg, ex_pc_branch;
+
+output reg out_flush_jump, out_flush_branch;
+output reg[31:0] out_pc;
+
+reg isbranch;
+
+initial begin
+	isbranch = 1'b0;
+	out_flush_jump = 1'b0;
+	out_flush_branch = 1'b0;
+	out_pc = 32'h00000000;
+end
+
+always @(negedge clk) begin
+	if(isbranch == 1'b1) begin
+		if(ex_branchsignal == 1'b1) begin
+			out_pc = ex_pc_branch;
+			out_flush_branch = 1'b1;
+		end
+		isbranch = 1'b0;
+	end else begin
+		out_flush_branch = 1'b0;
+
+		if(ctrl_jump == 1'b1) begin
+			out_flush_jump = 1'b1;
+			out_pc = (ctrl_jumpreg == 1'b0) ? pc_jump : pc_jumpreg;
+		end else if(ctrl_branch != 3'b000) isbranch = 1'b1;
+		else out_flush_jump = 1'b0;
+	end
+end
+endmodule

@@ -4,7 +4,7 @@ input[31:0] address;
 output reg[31:0] instruction;
 
 reg[31:0] instr_mem[127:0];
-
+/*
 initial begin
 instr_mem[0] = 32'd0;
 instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
@@ -17,17 +17,16 @@ instr_mem[7] = 32'b00100100000010010000000000000001;		// addi, $0 $9 1
 instr_mem[8] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
 instr_mem[9] = 32'd0;
 end
-/*
-initial begin
-out_clk = 1'b0;
+*/
 
+initial begin
 instr_mem[0] = 32'd0;
 instr_mem[1] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
 instr_mem[2] = 32'b00100101000010000000000011111111;		// addi, $8 $8 255
 instr_mem[3] = 32'b00000001000010000100100000100000;		// add, $8 $8 $9
 instr_mem[4] = 32'b00000001000000000101000000100000;		// add, $8 $0 $10
 instr_mem[5] = 32'b00010001000010100000000000000001;		// beq, $8 $10 +1
-instr_mem[6] = 32'd0;
+instr_mem[6] = 32'b00000001000000000111100000100000;		// add, $8 $0 $15
 instr_mem[7] = 32'b00000001000010010000000000011000;		// mult, $8 $9
 instr_mem[8] = 32'd0;
 instr_mem[9] = 32'b00000000000000000110000000010000;		// mfhi, $12
@@ -36,10 +35,10 @@ instr_mem[11] = 32'b10101100000011010000000000111100;		// sw, $0 $13 60
 instr_mem[12] = 32'd0;
 instr_mem[13] = 32'b00010001000010110000000000000001;		// beq, $8 $11 +1
 instr_mem[14] = 32'b10001100000000010000000000111100;		// lw, $0 $1 60
-instr_mem[15] = 32'd0;
+instr_mem[15] = 32'b00001100000000000000000000010000;		// jal, 16
 instr_mem[16] = 32'b00000000000000000000000000001000;		// jr, $0
 end
-*/
+
 always @ (*) begin
 	instruction = instr_mem[address/4];
 end

-D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module test
--- Compiling module testA
--- Compiling module testB
--- Compiling module testPC
-
-Top level modules:
-	test
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
-Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
--- Compiling module testbench
-
-Top level modules:
-	testbench
-
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
+D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Adder
 
@@ -65,12 +48,14 @@ Top level modules:
 	MEM_WB
 	PCcounter
 
-} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
+} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
 -- Compiling module Stall
+-- Compiling module Flush
 
 Top level modules:
 	Stall
+	Flush
 
 } {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
 Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015

@@ -3,12 +3,13 @@ module MIPS_Pipeline;
 
 wire clk;
 wire stallsignal;
-wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;		
+wire flush_jump, flush_branch;
+wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC, flush_pc;
 
 wire[31:0] instr;						// loaded instruction.
 
-wire[4:0] reg_writereg1;					// register number for the write data.
-wire[31:0] reg_writedata;					// data that will be written in the register.
+wire[4:0] temp_writereg, reg_writereg1;				// register number for the write data.
+wire[31:0] temp_writedata, reg_writedata;			// data that will be written in the register.
 wire[31:0] reg_readdata1, reg_readdata2;			// data from the requested register.
 
 wire[31:0] alu_input2;						// input data of ALU.
@@ -17,7 +18,7 @@ wire[5:0] alu_branch;						// indicator for branch operation.
 
 wire[31:0] mem_readdata;					// data from the requested address.
 
-wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
+wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
 wire[3:0] ctrl_aluctrl;						// control signals.
 wire[2:0] ctrl_branch;
 
@@ -31,75 +32,78 @@ wire[31:0] ifid_instr, ifid_PC_4;
 
 // ID_EX register outputs
 wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
-wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg;
+wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg, idex_link;
 wire[3:0] idex_aluctrl; 
 wire[2:0] idex_branch;
 wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;
 
 // EX_MEM register outputs
 wire[4:0] exmem_writereg1;
-wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump;
+wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link;
 wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;
 
 // MEM_WB register outputs
 wire[4:0] memwb_writereg1;
-wire memwb_regwrite, memwb_memtoreg, memwb_jump;
-wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump;
+wire memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link;
+wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch;
 
-
-
-wire tempstall;
-assign tempstall = 1'b0;
+wire temp;
+assign temp = 1'b0;
 
 Clock clock(clk);
-PCcounter pccounter(clk, stallsignal, nextPC, instr_address);
-Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, 
-	ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1,  
-	stallsignal);
+PCcounter pccounter(clk, stallsignal, (flush_jump|flush_branch), flush_pc, instr_address);
+Stall stall(clk, idex_regwrite, exmem_regwrite, memwb_regwrite, ifid_instr[25:21], ifid_instr[20:16], idex_writereg1, exmem_writereg1, memwb_writereg1, stallsignal);
+Flush flush(clk, ctrl_jump, ctrl_jumpreg, ctrl_branch, branch_signal, {ifid_PC_4[31:28], shiftJump_output[27:0]}, reg_readdata1, addPCbranch, 
+	flush_jump, flush_branch, flush_pc);
 
 // Instruction Fetch
 InstructionMemory instrmem(instr_address, instr);
 Adder add_pc4(instr_address, 32'h00000004, addPC4);
 
-IF_ID ifid(clk, stallsignal, instr, addPC4, 
+IF_ID ifid(clk, stallsignal, 
+	(flush_jump|flush_branch), instr, addPC4, 
 	ifid_instr, ifid_PC_4);
 
 // Instruction Decode
-Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
-Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11],  ctrl_regdst,  reg_writereg1);
+Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], 
+	ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);
+Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11],  ctrl_regdst,  temp_writereg);
+Mux5bit mux_link_reg(temp_writereg, 5'b11111,  ctrl_link,  reg_writereg1);
 Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata,  memwb_regwrite,  reg_readdata1, reg_readdata2);
 SignExtend extend(ifid_instr[15:0], extend_output);
 ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
 
-ID_EX idex(clk, stallsignal, reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, 
+ID_EX idex(clk, stallsignal, flush_branch, 
+	reg_writereg1, ifid_instr[25:21], ifid_instr[20:16], ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link, 
 	reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, 
-	idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, 
+	idex_writereg1, idex_readreg_num1, idex_readreg_num2, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg, idex_link, 
 	idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump);
 
 // Execute
 Mux32bit mux_alusrc(idex_readdata2, idex_extenddata,  idex_alusrc,  alu_input2);
 ALU alu(clk, idex_readdata1, alu_input2,  idex_aluctrl,  alu_result, alu_branch);
 ShiftLeft2 shiftBranch(idex_extenddata, shiftBranch_output);
-Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch);
+Adder add_branch(idex_PC_4, shiftBranch_output, addPCbranch);
 MuxBranchSignal mux_branchsignal(alu_branch,  idex_branch,  branch_signal);
 Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1,  idex_jumpreg,  tempPC_jump);
 
-EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, 
+EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump, idex_link, 
 	alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch, 
-	exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, 
+	exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump, exmem_link, 
 	exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
 
 // Memory
 DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata,  exmem_memread, exmem_memwrite,  mem_readdata);
 Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch,  exmem_branch ,  tempPC_branch);
 
-MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, 
-	exmem_aluresult, mem_readdata, exmem_PCjump, tempPC_branch, 
-	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, 
-	memwb_aluresult, memwb_memreaddata, memwb_PCjump, memwb_PCbranch);
+MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump, exmem_link, 
+	exmem_aluresult, mem_readdata, exmem_PC_4, exmem_PCjump, tempPC_branch, 
+	memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump, memwb_link, 
+	memwb_aluresult, memwb_memreaddata, memwb_PC_4, memwb_PCjump, memwb_PCbranch);
 
 // Writeback
-Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  reg_writedata);
+Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata,  memwb_memtoreg,  temp_writedata);
+Mux32bit mux_link_data(temp_writedata, memwb_PC_4,  memwb_link,  reg_writedata);
 Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump,  memwb_jump,  nextPC);
 
 

@@ -7,8 +7,8 @@ wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
 
 wire[31:0] instr;							// loaded instruction.
 
-wire[4:0] reg_writereg1;						// register number for the write data.
-wire[31:0] reg_writedata;						// data that will be written in the register.
+wire[4:0] temp_writereg, reg_writereg1;					// register number for the write data.
+wire[31:0] temp_writedata, reg_writedata;				// data that will be written in the register.
 wire[31:0] reg_readdata1, reg_readdata2;				// data from the requested register.
 
 wire[31:0] alu_input2;							// input data of ALU.
@@ -17,7 +17,7 @@ wire[5:0] alu_branch;							// indicator for branch operation.
 
 wire[31:0] mem_readdata;						// data from the requested address.
 
-wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
+wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, ctrl_link, branch_signal;
 wire[3:0] ctrl_aluctrl;
 wire[2:0] ctrl_branch;							// control signals.
 
@@ -32,12 +32,14 @@ InstructionMemory instrmem(instr_address, instr);
 Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata,  ctrl_regwrite,  reg_readdata1, reg_readdata2);
 ALU alu(clk, reg_readdata1, alu_input2,  ctrl_aluctrl,  alu_result, alu_branch);
 DataMemory datamem(clk, alu_result, reg_readdata2,  ctrl_memread, ctrl_memwrite,  mem_readdata);
-Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
+Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg, ctrl_link);
 
-Mux5bit mux_regdst(instr[20:16], instr[15:11],  ctrl_regdst,  reg_writereg1);
+Mux5bit mux_regdst(instr[20:16], instr[15:11],  ctrl_regdst,  temp_writereg);
+Mux5bit mux_link_reg(temp_writereg, 5'b11111,  ctrl_link,  reg_writereg1);
 MuxBranchSignal mux_branchsignal(alu_branch,  ctrl_branch,  branch_signal);
 Mux32bit mux_alusrc(reg_readdata2, extend_output,  ctrl_alusrc,  alu_input2);
-Mux32bit mux_memtoreg(alu_result, mem_readdata,  ctrl_memtoreg,  reg_writedata);
+Mux32bit mux_memtoreg(alu_result, mem_readdata,  ctrl_memtoreg,  temp_writedata);
+Mux32bit mux_link_data(temp_writedata, addPC4,  ctrl_link,  reg_writedata);
 Mux32bit mux_branch(addPC4, addPCbranch,  branch_signal ,  tempPC_branch);
 Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1,  ctrl_jumpreg,  tempPC_jump);
 Mux32bit mux_jump(tempPC_branch, tempPC_jump,  ctrl_jump,  nextPC);

-module IF_ID(clk, stall, in_instruction, in_PC_4, 
+module IF_ID(clk, stall, flush, in_instruction, in_PC_4, 
 	out_instruction, out_PC_4);
-input clk, stall;
+input clk, stall, flush;
 
 input[31:0] in_instruction, in_PC_4;
 
@@ -8,65 +8,72 @@ output reg[31:0] out_instruction, out_PC_4;
 
 reg[31:0] temp_instruction, temp_PC_4;
 
-reg stallfinished;
+reg first, stallfinished, flushed;
 
 initial begin
+	first = 1'b1;
 	stallfinished = 1'b0;
+	flushed = 1'b0;
 end
-
 always @(posedge clk) begin
-
 	if(stall == 1'b1) begin
+		out_instruction <= temp_instruction;
+		out_PC_4 <= temp_PC_4;		
+	end
+	else if(flush == 1'b1) begin
 		out_instruction <= 32'h00000000;
 		out_PC_4 <= 32'h00000000;
 	end
+	else if(flushed == 1'b1) begin
+		out_instruction <= 32'h00000000;
+		out_PC_4 <= 32'h00000000;
+		stallfinished = 1'b0;
+		flushed = 1'b0;
+	end
 	else if(stallfinished == 1'b1) begin
 		out_instruction <= temp_instruction;
 		out_PC_4 <= temp_PC_4;		
-		
 		stallfinished = 1'b0;
+		flushed = 1'b0;
 	end
 	else begin
 		out_instruction <= in_instruction;
 		out_PC_4 <= in_PC_4;
 	end
 end
-
 always @(posedge stall) begin
 	temp_instruction <= out_instruction;
 	temp_PC_4 <= out_PC_4;
 end
-always @(negedge stall) begin
-	stallfinished = 1'b1;
-end
+always @(negedge stall) stallfinished = 1'b1;
+always @(negedge flush) flushed = 1'b1;
 endmodule
 
 
-module ID_EX(clk, stall, in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 
+module ID_EX(clk, stall, flush, 
+	in_writereg_num, in_readreg_num1, in_readreg_num2, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, in_link, 
 	in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, 
-	out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 
+	out_writereg_num, out_readreg_num1, out_readreg_num2, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, out_link, 
 	out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump);
-input clk, stall;
+input clk, stall, flush;
 
 input[4:0] in_writereg_num, in_readreg_num1, in_readreg_num2;
-input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg;
+input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_jump, in_jumpreg, in_link;
 input[3:0] in_aluctrl;
 input[2:0] in_branch;
 input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump;
 
 output reg[4:0] out_writereg_num, out_readreg_num1, out_readreg_num2;
-output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg;
+output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_jump, out_jumpreg, out_link;
 output reg[3:0] out_aluctrl;
 output reg[2:0] out_branch;
 output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump;
 
 reg stallfinished;
 
-initial begin
-	stallfinished = 1'b0;
-end
+initial stallfinished = 1'b0;
 always @(posedge clk) begin
-	if(stall == 1'b1) begin
+	if(stall == 1'b1 || flush == 1'b1) begin
 		out_writereg_num <= 5'b00000;
 		out_readreg_num1 <= 5'b00000;
 		out_readreg_num2 <= 5'b00000;
@@ -80,6 +87,7 @@ always @(posedge clk) begin
 		out_branch <= 3'b000;
 		out_jump <= 1'b0;
 		out_jumpreg <= 1'b0;
+		out_link <= 1'b0;
 
 		out_readdata1 <= 32'h00000000;
 		out_readdata2 <= 32'h00000000;
@@ -101,6 +109,7 @@ always @(posedge clk) begin
 		out_branch <= 3'b000;
 		out_jump <= 1'b0;
 		out_jumpreg <= 1'b0;
+		out_link <= 1'b0;
 
 		out_readdata1 <= 32'h00000000;
 		out_readdata2 <= 32'h00000000;
@@ -124,6 +133,7 @@ always @(posedge clk) begin
 		out_branch <= in_branch;
 		out_jump <= in_jump;
 		out_jumpreg <= in_jumpreg;
+		out_link <= in_link;
 
 		out_readdata1 <= in_readdata1;
 		out_readdata2 <= in_readdata2;
@@ -132,24 +142,21 @@ always @(posedge clk) begin
 		out_tempPCjump <= in_tempPCjump;
 	end
 end
-always @(negedge stall) begin
-	stallfinished = 1'b1;
-end
-
+always @(negedge stall or negedge flush) stallfinished = 1'b1;
 endmodule
 
 
-module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, 
+module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link, 
 	in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch, 
-	out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 
+	out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_link, 
 	out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
 input clk;
 
 input[4:0] in_writereg_num;
-input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
+input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_link;
 input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
 output reg[4:0] out_writereg_num;
-output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump;
+output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_link;
 output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;
 
 always @(posedge clk) begin
@@ -160,6 +167,7 @@ always @(posedge clk) begin
 	out_memtoreg <= in_memtoreg;
 	out_branch <= in_branch;
 	out_jump <= in_jump;
+	out_link <= in_link;
 
 	out_aluresult <= in_aluresult;
 	out_mem_writedata <= in_mem_writedata;
@@ -170,33 +178,35 @@ end
 endmodule
 
 
-module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 
-	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCjump, out_PCbranch);
+module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_link, in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch, 
+	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_link, out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch);
 input clk;
 
 input[4:0] in_writereg_num;
-input in_regwrite, in_memtoreg, in_jump;
-input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
+input in_regwrite, in_memtoreg, in_jump, in_link;
+input[31:0] in_aluresult, in_memreaddata, in_PC_4, in_PCjump, in_PCbranch;
 output reg[4:0] out_writereg_num;
-output reg out_regwrite, out_memtoreg, out_jump;
-output reg[31:0] out_aluresult, out_memreaddata, out_PCbranch, out_PCjump;
+output reg out_regwrite, out_memtoreg, out_jump, out_link;
+output reg[31:0] out_aluresult, out_memreaddata, out_PC_4, out_PCjump, out_PCbranch;
 
 always @(posedge clk) begin
 	out_writereg_num <= in_writereg_num;
 	out_regwrite <= in_regwrite;
 	out_memtoreg <= in_memtoreg;
 	out_jump <= in_jump;
+	out_link <= in_link;
 
 	out_aluresult <= in_aluresult;
 	out_memreaddata <= in_memreaddata;
+	out_PC_4 <= in_PC_4;
 	out_PCjump <= in_PCjump;
 	out_PCbranch <= in_PCbranch;
 end
 endmodule
 
 /* Not Finished */
-module PCcounter(clk, stall, in_pc, out_nextpc);
-input clk, stall;
+module PCcounter(clk, stall, flush, in_pc, out_nextpc);
+input clk, stall, flush;
 
 input[31:0] in_pc;
 output reg[31:0] out_nextpc;
@@ -210,12 +220,10 @@ initial begin
 end
 
 always @(posedge clk) begin
-	
 	if(stallfinished == 1'b1) stallfinished = 1'b0;
-	else if(stall == 1'b0) PC = PC+4;
+	else if(stall == 1'b0 && flush == 1'b0) PC = PC+4;
 	out_nextpc = PC;
 end
-always @(negedge stall) begin
-	stallfinished = 1'b1;
-end
+always @(negedge stall or negedge flush) stallfinished = 1'b1;
+always @(posedge flush) PC = in_pc;
 endmodule

@@ -9,7 +9,7 @@ z2
 cModel Technology
 dC:/Modeltech_pe_edu_10.4a/examples
 vAdder
-Z0 !s110 1591621209
+Z0 !s110 1591983139
 !i10b 1
 !s100 LKl?GBS:oo[A[hLP0Qb^_1
 IlbJEP?2C3Ya>zhzD12^S]1
@@ -23,7 +23,7 @@ Z3 OP;L;10.4a;61
 r1
 !s85 0
 31
-Z4 !s108 1591621208.000000
+Z4 !s108 1591983139.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
 !s101 -O0
@@ -45,7 +45,7 @@ R3
 r1
 !s85 0
 31
-Z6 !s108 1591621209.000000
+R4
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
 !s101 -O0
@@ -67,7 +67,7 @@ R3
 r1
 !s85 0
 31
-R6
+R4
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v|
 !s101 -O0
@@ -75,13 +75,13 @@ R6
 R5
 n@clock
 vControl
-R0
+Z6 !s110 1591983140
 !i10b 1
-!s100 4N9S2_;3jCoh7S5CM:UBB2
-IiJiDhRWdHkEd649hCz4P;1
+!s100 NdQKEjPCPSHG<0<4CTgfz1
+Io?;>IIVLB=Zl;M_TSQZ9I2
 R1
 R2
-w1591452194
+w1591975942
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
 L0 1
@@ -89,7 +89,7 @@ R3
 r1
 !s85 0
 31
-R6
+R4
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
 !s101 -O0
@@ -97,7 +97,7 @@ R6
 R5
 n@control
 vDataMemory
-R0
+R6
 !i10b 1
 !s100 e=5E[GS05J<RCdT=KSMX_1
 I9=L>R4ccfGY8^T;U50LY?1
@@ -111,7 +111,7 @@ R3
 r1
 !s85 0
 31
-R6
+Z7 !s108 1591983140.000000
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
 !s101 -O0
@@ -119,79 +119,101 @@ R6
 R5
 n@data@memory
 vEX_MEM
-Z7 !s110 1591621210
+Z8 !s110 1591983141
 !i10b 1
-!s100 7M;f[J6l]Q8I7]G9EaW4b2
-I4[]:7KKT=g2:;MLnikc863
+!s100 ^^:n;T<R5`c:oReRzT=QT3
+IUKd^A=OJc08kD[zWg_`SA2
 R1
 R2
-Z8 w1591621089
-Z9 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-Z10 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
-L0 142
+Z9 w1591982553
+Z10 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+Z11 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
+L0 149
 R3
 r1
 !s85 0
 31
-Z11 !s108 1591621210.000000
-Z12 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
-Z13 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+Z12 !s108 1591983141.000000
+Z13 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
+Z14 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
 !s101 -O0
 !i113 1
 R5
 n@e@x_@m@e@m
-vID_EX
-R7
+vFlush
+R6
 !i10b 1
-!s100 id94:21DzMBedgX<6MLIW3
-ILTL53m=Ci^KdWXiJ:6G`E2
+!s100 G^dZ>]FGe3h^`=G1P?aLA1
+IaJUhT0Va;e^W1QK:FQaQi2
 R1
 R2
+Z15 w1591970913
+Z16 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+Z17 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
+L0 26
+R3
+r1
+!s85 0
+31
+R7
+Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
+!s101 -O0
+!i113 1
+R5
+n@flush
+vID_EX
 R8
+!i10b 1
+!s100 ?MgFelQ<oVo:WHdjbIKo00
+ITSSi3aWmi:I7boRWd[i>H3
+R1
+R2
 R9
 R10
-L0 45
+R11
+L0 53
 R3
 r1
 !s85 0
 31
-R11
 R12
 R13
+R14
 !s101 -O0
 !i113 1
 R5
 n@i@d_@e@x
 vIF_ID
-R7
+R8
 !i10b 1
-!s100 ?M?9X@=b^flc3blH:Dn^g2
-I^7T81LjBP2[g8ie`ATZ=G2
+!s100 bEXSIWd8gnI`]GAUe_N>70
+IRmIoA42QB9iZ_NYh`X79>3
 R1
 R2
-R8
 R9
 R10
+R11
 L0 1
 R3
 r1
 !s85 0
 31
-R11
 R12
 R13
+R14
 !s101 -O0
 !i113 1
 R5
 n@i@f_@i@d
 vInstructionMemory
-R7
+R6
 !i10b 1
-!s100 <VK`==0E@Llng:<adzYd80
-I6V??0<R5lO5JZ[eh2?Qo13
+!s100 dUP:<mGld?9A^?GbR`HX41
+Ijoe6hdS43:Kg7S<nf[6_S3
 R1
 R2
-w1591579676
+w1591979413
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
 L0 1
@@ -199,7 +221,7 @@ R3
 r1
 !s85 0
 31
-R11
+R7
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
 !s101 -O0
@@ -207,35 +229,35 @@ R11
 R5
 n@instruction@memory
 vMEM_WB
-R7
+R8
 !i10b 1
-!s100 [HWKoHB:zC]dGeW[NDE]30
-IEjo6PSl[2V[fN=O@DA7W_0
+!s100 9m=P24TTjNA?g>P@e6;[=2
+I3VBN<k:`mX_jIkFWMoi3a2
 R1
 R2
-R8
 R9
 R10
-L0 173
+R11
+L0 181
 R3
 r1
 !s85 0
 31
-R11
 R12
 R13
+R14
 !s101 -O0
 !i113 1
 R5
 n@m@e@m_@w@b
 vMIPS_Pipeline
-R7
+R6
 !i10b 1
-!s100 O:NALVmB^PBj5HkG<@2XA3
-I5L3]J:Nz<PQZe=N8z]::o3
+!s100 AkG9Fhg`zlP55C:McA:FM2
+IZRIYdAdZBSFN3o<CV_WgK0
 R1
 R2
-w1591621120
+w1591980998
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
 L0 2
@@ -243,7 +265,7 @@ R3
 r1
 !s85 0
 31
-R11
+R7
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
 !s101 -O0
@@ -251,13 +273,13 @@ R11
 R5
 n@m@i@p@s_@pipeline
 vMIPS_SingleCycle
-R7
+R8
 !i10b 1
-!s100 Zz<Q962j57a4IzW0mQ=5=1
-IMJcJ>deKe`cm>JGo56D8H2
+!s100 ;_UzWlV_FikM_gED@zTjP2
+IQEAV;clN[65lKfZREk<=Q1
 R1
 R2
-w1591531598
+w1591976493
 8D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 FD:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
 L0 1
@@ -265,7 +287,7 @@ R3
 r1
 !s85 0
 31
-R11
+R7
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
 !s101 -O0
@@ -273,95 +295,95 @@ R11
 R5
 n@m@i@p@s_@single@cycle
 vMux32bit
-R7
+R8
 !i10b 1
 !s100 foJG^YU75_eND1Og;6Z>O1
 II3=gjhQD0_cn8mlDL]@bi1
 R1
 R2
-Z14 w1591452448
-Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
-Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Z20 w1591452448
+Z21 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
+Z22 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
 L0 15
 R3
 r1
 !s85 0
 31
-R11
-Z17 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
-Z18 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+R12
+Z23 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
+Z24 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
 !s101 -O0
 !i113 1
 R5
 n@mux32bit
 vMux5bit
-R7
+R8
 !i10b 1
 !s100 oSd=[kHDJb<:G7LN4]6@e3
 IfiVXg_aB2GQG7?F@=HcEi0
 R1
 R2
-R14
-R15
-R16
+R20
+R21
+R22
 L0 1
 R3
 r1
 !s85 0
 31
-R11
-R17
-R18
+R12
+R23
+R24
 !s101 -O0
 !i113 1
 R5
 n@mux5bit
 vMuxBranchSignal
-R7
+R8
 !i10b 1
 !s100 H1RKS9h`Y6QFX88CRc<g[0
 IGJT?gXMKEEWH?G^lPN79V2
 R1
 R2
-R14
-R15
-R16
+R20
+R21
+R22
 L0 29
 R3
 r1
 !s85 0
 31
-R11
-R17
-R18
+R12
+R23
+R24
 !s101 -O0
 !i113 1
 R5
 n@mux@branch@signal
 vPCcounter
-R7
+R8
 !i10b 1
-!s100 bjm68NMba>Y8oFGU?RHPK0
-IU;F]_bg19=g^Z:GGm6U:71
+!s100 WeKa=V6mT9ZlU8@mTC`g42
+Il_T>dO3a82KCcjIcT0_8<0
 R1
 R2
-R8
 R9
 R10
-L0 198
+R11
+L0 208
 R3
 r1
 !s85 0
 31
-R11
 R12
 R13
+R14
 !s101 -O0
 !i113 1
 R5
 n@p@ccounter
 vRegister
-Z19 !s110 1591621211
+R8
 !i10b 1
 !s100 bC`<7GaPg=bDaZoUR<ADa0
 I<aR5RJ2c1Qba>GdC]KZCd2
@@ -375,7 +397,7 @@ R3
 r1
 !s85 0
 31
-Z20 !s108 1591621211.000000
+R12
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
 !s101 -O0
@@ -383,7 +405,7 @@ Z20 !s108 1591621211.000000
 R5
 n@register
 vShiftLeft2
-R19
+R8
 !i10b 1
 !s100 ]Zje9D[f?jFRnJBn`OeHc1
 I]0TYJ]_7?FkOoY=2GlT5=3
@@ -397,7 +419,7 @@ R3
 r1
 !s85 0
 31
-R20
+R12
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
 !s101 -O0
@@ -405,7 +427,7 @@ R20
 R5
 n@shift@left2
 vSignExtend
-R19
+R0
 !i10b 1
 !s100 =4eXcc0im3]S=Kk@o:eh32
 IFBiMm>fY8WE23A[Ye;CUj3
@@ -419,7 +441,7 @@ R3
 r1
 !s85 0
 31
-R20
+R4
 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v|
 !s101 -O0
@@ -427,132 +449,24 @@ R20
 R5
 n@sign@extend
 vStall
-R19
+R6
 !i10b 1
-!s100 N?ZClBzVEP54JoYb>Ao9:3
-I:YbV=h@`DImW@Qc>>HXoc3
+!s100 z^N=>UeP;k2mNYmKnG`WR2
+IOg[[<<GgT4k[<hhzADXMC3
 R1
 R2
-w1591618522
-8D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
-FD:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v
-L0 1
+R15
+R16
+R17
+L0 2
 R3
 r1
 !s85 0
 31
-R20
-!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Stall.v|
+R7
+R18
+R19
 !s101 -O0
 !i113 1
 R5
 n@stall
-vtest
-Z21 !s110 1591621212
-!i10b 1
-!s100 KKL;hoG0Ojk_U;6H:]ViZ1
-Im`S61;3SN3Jlg_1AeFCP@3
-R1
-R2
-Z22 w1591501317
-Z23 8D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
-Z24 FD:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
-L0 1
-R3
-r1
-!s85 0
-31
-R20
-Z25 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
-Z26 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v|
-!s101 -O0
-!i113 1
-R5
-vtestA
-R21
-!i10b 1
-!s100 Pkg?M_BZm@c5Y24EY;_H^3
-InVhi@1kAoF`f3N_KB]^7i3
-R1
-R2
-R22
-R23
-R24
-L0 24
-R3
-r1
-!s85 0
-31
-R20
-R25
-R26
-!s101 -O0
-!i113 1
-R5
-ntest@a
-vtestB
-R21
-!i10b 1
-!s100 S@=1_l7e?W`b88GB`bZQS0
-Il?;09cMF7Oe7LY1h4do2M3
-R1
-R2
-R22
-R23
-R24
-L0 55
-R3
-r1
-!s85 0
-31
-R20
-R25
-R26
-!s101 -O0
-!i113 1
-R5
-ntest@b
-vtestbench
-!s110 1591621208
-!i10b 1
-!s100 OS>9h:91ecFHGVTRNVN]_2
-IR?_j2LXMem;jJUiXH@MhI0
-R1
-R2
-w1590428983
-8D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
-FD:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
-L0 1
-R3
-r1
-!s85 0
-31
-R4
-!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
-!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v|
-!s101 -O0
-!i113 1
-R5
-vtestPC
-R21
-!i10b 1
-!s100 L_L<o7@FSVAPYd[5blZAI1
-I8O06UXYD2fBn2meXg:jBC3
-R1
-R2
-R22
-R23
-R24
-L0 79
-R3
-r1
-!s85 0
-31
-R20
-R25
-R26
-!s101 -O0
-!i113 1
-R5
-ntest@p@c