branch-limits-fp-mips.mir
7 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MIPS
# RUN: llc -mtriple=mips-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
# Test the long branch expansion of various branches
--- |
define i32 @a(double %a, double %b) {
entry:
%cmp = fcmp une double %a, %b
br i1 %cmp, label %if.then, label %return
if.then:
call void asm sideeffect ".space 310680", "~{$1}"()
ret i32 0
return:
ret i32 1
}
define i32 @b(double %a, double %b) {
entry:
%cmp = fcmp une double %a, %b
br i1 %cmp, label %if.then, label %return
if.then:
call void asm sideeffect ".space 310680", "~{$1}"()
ret i32 0
return:
ret i32 1
}
...
---
name: a
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$d6', virtual-reg: '' }
- { reg: '$d7', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS-LABEL: name: a
; MIPS: bb.0.entry:
; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
; MIPS: BC1F $fcc0, %bb.2, implicit-def $at {
; MIPS: NOP
; MIPS: }
; MIPS: bb.1.entry:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: J %bb.3, implicit-def $at {
; MIPS: NOP
; MIPS: }
; MIPS: bb.2.if.then:
; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
; MIPS: $v0 = ADDiu $zero, 0
; MIPS: }
; MIPS: bb.3.return:
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
; MIPS: $v0 = ADDiu $zero, 1
; MIPS: }
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
; PIC: BC1F $fcc0, %bb.3, implicit-def $at {
; PIC: NOP
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0
; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d6, $d7
FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
BC1T killed $fcc0, %bb.2, implicit-def $at
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
$v0 = ADDiu $zero, 0
PseudoReturn undef $ra, implicit killed $v0
bb.2.return:
$v0 = ADDiu $zero, 1
PseudoReturn undef $ra, implicit killed $v0
...
---
name: b
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$d6', virtual-reg: '' }
- { reg: '$d7', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS-LABEL: name: b
; MIPS: bb.0.entry:
; MIPS: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; MIPS: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
; MIPS: BC1T $fcc0, %bb.2, implicit-def $at {
; MIPS: NOP
; MIPS: }
; MIPS: bb.1.entry:
; MIPS: successors: %bb.3(0x80000000)
; MIPS: J %bb.3, implicit-def $at {
; MIPS: NOP
; MIPS: }
; MIPS: bb.2.if.then:
; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
; MIPS: $v0 = ADDiu $zero, 0
; MIPS: }
; MIPS: bb.3.return:
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
; MIPS: $v0 = ADDiu $zero, 1
; MIPS: }
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
; PIC: BC1T $fcc0, %bb.3, implicit-def $at {
; PIC: NOP
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0
; PIC: JR $at {
; PIC: $sp = ADDiu $sp, 8
; PIC: }
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d6, $d7
FCMP_D32 killed renamable $d6, killed renamable $d7, 2, implicit-def $fcc0
BC1F killed $fcc0, %bb.2, implicit-def $at
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
$v0 = ADDiu $zero, 0
PseudoReturn undef $ra, implicit killed $v0
bb.2.return:
$v0 = ADDiu $zero, 1
PseudoReturn undef $ra, implicit killed $v0
...