branch-limits-fp-mipsr6.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=R6
# RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
# Test the long branch expansion of various branches
--- |
define i32 @a(double %a, double %b) {
entry:
%cmp = fcmp une double %a, %b
br i1 %cmp, label %if.then, label %return
if.then: ; preds = %entry
call void asm sideeffect ".space 310680", "~{$1}"()
ret i32 0
return: ; preds = %entry
ret i32 1
}
define i32 @b(double %a, double %b) {
entry:
%cmp = fcmp ueq double %a, %b
br i1 %cmp, label %if.then, label %return
if.then: ; preds = %entry
call void asm sideeffect ".space 310680", "~{$1}"()
ret i32 0
return: ; preds = %entry
ret i32 1
}
...
---
name: a
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$d12_64', virtual-reg: '' }
- { reg: '$d14_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; R6-LABEL: name: a
; R6: bb.0.entry:
; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
; R6: BC1NEZ $d0_64, %bb.2 {
; R6: NOP
; R6: }
; R6: bb.1.entry:
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
; R6: bb.2.if.then:
; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; R6: PseudoReturn undef $ra, implicit killed $v0 {
; R6: $v0 = ADDiu $zero, 0
; R6: }
; R6: bb.3.return:
; R6: PseudoReturn undef $ra, implicit killed $v0 {
; R6: $v0 = ADDiu $zero, 1
; R6: }
; PIC-LABEL: name: a
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
; PIC: BC1NEZ $d0_64, %bb.3 {
; PIC: NOP
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d12_64, $d14_64
$f0 = CMP_EQ_D killed $d12_64, killed $d14_64
BC1EQZ killed $d0_64, %bb.2, implicit-def $at
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
$v0 = ADDiu $zero, 0
PseudoReturn undef $ra, implicit killed $v0
bb.2.return:
$v0 = ADDiu $zero, 1
PseudoReturn undef $ra, implicit killed $v0
...
---
name: b
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$d12_64', virtual-reg: '' }
- { reg: '$d14_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; R6-LABEL: name: b
; R6: bb.0.entry:
; R6: successors: %bb.2(0x50000000), %bb.1(0x30000000)
; R6: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
; R6: BC1EQZ $d0_64, %bb.2 {
; R6: NOP
; R6: }
; R6: bb.1.entry:
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
; R6: bb.2.if.then:
; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; R6: PseudoReturn undef $ra, implicit killed $v0 {
; R6: $v0 = ADDiu $zero, 0
; R6: }
; R6: bb.3.return:
; R6: PseudoReturn undef $ra, implicit killed $v0 {
; R6: $v0 = ADDiu $zero, 1
; R6: }
; PIC-LABEL: name: b
; PIC: bb.0.entry:
; PIC: successors: %bb.3(0x50000000), %bb.1(0x30000000)
; PIC: $f0 = CMP_EQ_D killed $d12_64, killed $d14_64
; PIC: BC1EQZ $d0_64, %bb.3 {
; PIC: NOP
; PIC: }
; PIC: bb.1.entry:
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
; PIC: $at = ADDu $ra, $at
; PIC: $ra = LW $sp, 0
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then:
; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
; PIC: bb.4.return:
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 1
; PIC: }
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d12_64, $d14_64
$f0 = CMP_EQ_D killed $d12_64, killed $d14_64
BC1NEZ killed $d0_64, %bb.2, implicit-def $at
bb.1.if.then:
INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
$v0 = ADDiu $zero, 0
PseudoReturn undef $ra, implicit killed $v0
bb.2.return:
$v0 = ADDiu $zero, 1
PseudoReturn undef $ra, implicit killed $v0
...