fast-isel-logic-op.ll
8.13 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; AND
define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {
; CHECK-LABEL: and_rr_i1
; CHECK: and [[REG:w[0-9]+]], w0, w1
%1 = and i1 %a, %b
ret i1 %1
}
define zeroext i8 @and_rr_i8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: and_rr_i8
; CHECK: and [[REG:w[0-9]+]], w0, w1
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
%1 = and i8 %a, %b
ret i8 %1
}
define zeroext i16 @and_rr_i16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: and_rr_i16
; CHECK: and [[REG:w[0-9]+]], w0, w1
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
%1 = and i16 %a, %b
ret i16 %1
}
define i32 @and_rr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: and_rr_i32
; CHECK: and w0, w0, w1
%1 = and i32 %a, %b
ret i32 %1
}
define i64 @and_rr_i64(i64 %a, i64 %b) {
; CHECK-LABEL: and_rr_i64
; CHECK: and x0, x0, x1
%1 = and i64 %a, %b
ret i64 %1
}
define zeroext i1 @and_ri_i1(i1 signext %a) {
; CHECK-LABEL: and_ri_i1
; CHECK: and {{w[0-9]+}}, w0, #0x1
%1 = and i1 %a, 1
ret i1 %1
}
define zeroext i8 @and_ri_i8(i8 signext %a) {
; CHECK-LABEL: and_ri_i8
; CHECK: and {{w[0-9]+}}, w0, #0xf
%1 = and i8 %a, 15
ret i8 %1
}
define zeroext i16 @and_ri_i16(i16 signext %a) {
; CHECK-LABEL: and_ri_i16
; CHECK: and {{w[0-9]+}}, w0, #0xff
%1 = and i16 %a, 255
ret i16 %1
}
define i32 @and_ri_i32(i32 %a) {
; CHECK-LABEL: and_ri_i32
; CHECK: and w0, w0, #0xff
%1 = and i32 %a, 255
ret i32 %1
}
define i64 @and_ri_i64(i64 %a) {
; CHECK-LABEL: and_ri_i64
; CHECK: and x0, x0, #0xff
%1 = and i64 %a, 255
ret i64 %1
}
define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: and_rs_i8
; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #4
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
%1 = shl i8 %b, 4
%2 = and i8 %a, %1
ret i8 %2
}
define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: and_rs_i16
; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #8
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
%1 = shl i16 %b, 8
%2 = and i16 %a, %1
ret i16 %2
}
define i32 @and_rs_i32(i32 %a, i32 %b) {
; CHECK-LABEL: and_rs_i32
; CHECK: and w0, w0, w1, lsl #8
%1 = shl i32 %b, 8
%2 = and i32 %a, %1
ret i32 %2
}
define i64 @and_rs_i64(i64 %a, i64 %b) {
; CHECK-LABEL: and_rs_i64
; CHECK: and x0, x0, x1, lsl #8
%1 = shl i64 %b, 8
%2 = and i64 %a, %1
ret i64 %2
}
define i32 @and_mul_i32(i32 %a, i32 %b) {
; CHECK-LABEL: and_mul_i32
; CHECK: and w0, w0, w1, lsl #2
%1 = mul i32 %b, 4
%2 = and i32 %a, %1
ret i32 %2
}
define i64 @and_mul_i64(i64 %a, i64 %b) {
; CHECK-LABEL: and_mul_i64
; CHECK: and x0, x0, x1, lsl #2
%1 = mul i64 %b, 4
%2 = and i64 %a, %1
ret i64 %2
}
; OR
define zeroext i1 @or_rr_i1(i1 signext %a, i1 signext %b) {
; CHECK-LABEL: or_rr_i1
; CHECK: orr [[REG:w[0-9]+]], w0, w1
%1 = or i1 %a, %b
ret i1 %1
}
define zeroext i8 @or_rr_i8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: or_rr_i8
; CHECK: orr [[REG:w[0-9]+]], w0, w1
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
%1 = or i8 %a, %b
ret i8 %1
}
define zeroext i16 @or_rr_i16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: or_rr_i16
; CHECK: orr [[REG:w[0-9]+]], w0, w1
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
%1 = or i16 %a, %b
ret i16 %1
}
define i32 @or_rr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: or_rr_i32
; CHECK: orr w0, w0, w1
%1 = or i32 %a, %b
ret i32 %1
}
define i64 @or_rr_i64(i64 %a, i64 %b) {
; CHECK-LABEL: or_rr_i64
; CHECK: orr x0, x0, x1
%1 = or i64 %a, %b
ret i64 %1
}
define zeroext i8 @or_ri_i8(i8 %a) {
; CHECK-LABEL: or_ri_i8
; CHECK: orr [[REG:w[0-9]+]], w0, #0xf
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
%1 = or i8 %a, 15
ret i8 %1
}
define zeroext i16 @or_ri_i16(i16 %a) {
; CHECK-LABEL: or_ri_i16
; CHECK: orr [[REG:w[0-9]+]], w0, #0xff
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
%1 = or i16 %a, 255
ret i16 %1
}
define i32 @or_ri_i32(i32 %a) {
; CHECK-LABEL: or_ri_i32
; CHECK: orr w0, w0, #0xff
%1 = or i32 %a, 255
ret i32 %1
}
define i64 @or_ri_i64(i64 %a) {
; CHECK-LABEL: or_ri_i64
; CHECK: orr x0, x0, #0xff
%1 = or i64 %a, 255
ret i64 %1
}
define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: or_rs_i8
; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #4
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
%1 = shl i8 %b, 4
%2 = or i8 %a, %1
ret i8 %2
}
define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: or_rs_i16
; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #8
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
%1 = shl i16 %b, 8
%2 = or i16 %a, %1
ret i16 %2
}
define i32 @or_rs_i32(i32 %a, i32 %b) {
; CHECK-LABEL: or_rs_i32
; CHECK: orr w0, w0, w1, lsl #8
%1 = shl i32 %b, 8
%2 = or i32 %a, %1
ret i32 %2
}
define i64 @or_rs_i64(i64 %a, i64 %b) {
; CHECK-LABEL: or_rs_i64
; CHECK: orr x0, x0, x1, lsl #8
%1 = shl i64 %b, 8
%2 = or i64 %a, %1
ret i64 %2
}
define i32 @or_mul_i32(i32 %a, i32 %b) {
; CHECK-LABEL: or_mul_i32
; CHECK: orr w0, w0, w1, lsl #2
%1 = mul i32 %b, 4
%2 = or i32 %a, %1
ret i32 %2
}
define i64 @or_mul_i64(i64 %a, i64 %b) {
; CHECK-LABEL: or_mul_i64
; CHECK: orr x0, x0, x1, lsl #2
%1 = mul i64 %b, 4
%2 = or i64 %a, %1
ret i64 %2
}
; XOR
define zeroext i1 @xor_rr_i1(i1 signext %a, i1 signext %b) {
; CHECK-LABEL: xor_rr_i1
; CHECK: eor [[REG:w[0-9]+]], w0, w1
%1 = xor i1 %a, %b
ret i1 %1
}
define zeroext i8 @xor_rr_i8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: xor_rr_i8
; CHECK: eor [[REG:w[0-9]+]], w0, w1
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
%1 = xor i8 %a, %b
ret i8 %1
}
define zeroext i16 @xor_rr_i16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: xor_rr_i16
; CHECK: eor [[REG:w[0-9]+]], w0, w1
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
%1 = xor i16 %a, %b
ret i16 %1
}
define i32 @xor_rr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: xor_rr_i32
; CHECK: eor w0, w0, w1
%1 = xor i32 %a, %b
ret i32 %1
}
define i64 @xor_rr_i64(i64 %a, i64 %b) {
; CHECK-LABEL: xor_rr_i64
; CHECK: eor x0, x0, x1
%1 = xor i64 %a, %b
ret i64 %1
}
define zeroext i8 @xor_ri_i8(i8 signext %a) {
; CHECK-LABEL: xor_ri_i8
; CHECK: eor [[REG:w[0-9]+]], w0, #0xf
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
%1 = xor i8 %a, 15
ret i8 %1
}
define zeroext i16 @xor_ri_i16(i16 signext %a) {
; CHECK-LABEL: xor_ri_i16
; CHECK: eor [[REG:w[0-9]+]], w0, #0xff
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
%1 = xor i16 %a, 255
ret i16 %1
}
define i32 @xor_ri_i32(i32 %a) {
; CHECK-LABEL: xor_ri_i32
; CHECK: eor w0, w0, #0xff
%1 = xor i32 %a, 255
ret i32 %1
}
define i64 @xor_ri_i64(i64 %a) {
; CHECK-LABEL: xor_ri_i64
; CHECK: eor x0, x0, #0xff
%1 = xor i64 %a, 255
ret i64 %1
}
define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {
; CHECK-LABEL: xor_rs_i8
; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #4
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}
%1 = shl i8 %b, 4
%2 = xor i8 %a, %1
ret i8 %2
}
define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {
; CHECK-LABEL: xor_rs_i16
; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #8
; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}
%1 = shl i16 %b, 8
%2 = xor i16 %a, %1
ret i16 %2
}
define i32 @xor_rs_i32(i32 %a, i32 %b) {
; CHECK-LABEL: xor_rs_i32
; CHECK: eor w0, w0, w1, lsl #8
%1 = shl i32 %b, 8
%2 = xor i32 %a, %1
ret i32 %2
}
define i64 @xor_rs_i64(i64 %a, i64 %b) {
; CHECK-LABEL: xor_rs_i64
; CHECK: eor x0, x0, x1, lsl #8
%1 = shl i64 %b, 8
%2 = xor i64 %a, %1
ret i64 %2
}
define i32 @xor_mul_i32(i32 %a, i32 %b) {
; CHECK-LABEL: xor_mul_i32
; CHECK: eor w0, w0, w1, lsl #2
%1 = mul i32 %b, 4
%2 = xor i32 %a, %1
ret i32 %2
}
define i64 @xor_mul_i64(i64 %a, i64 %b) {
; CHECK-LABEL: xor_mul_i64
; CHECK: eor x0, x0, x1, lsl #2
%1 = mul i64 %b, 4
%2 = xor i64 %a, %1
ret i64 %2
}