VEInstPrinter.cpp
3.55 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
//===-- VEInstPrinter.cpp - Convert VE MCInst to assembly syntax -----------==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an VE MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#include "VEInstPrinter.h"
#include "VE.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "ve-asmprinter"
// The generated AsmMatcher VEGenAsmWriter uses "VE" as the target
// namespace.
namespace llvm {
namespace VE {
using namespace VE;
}
} // namespace llvm
#define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR
#include "VEGenAsmWriter.inc"
void VEInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << '%' << StringRef(getRegisterName(RegNo)).lower();
}
void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) {
if (!printAliasInstr(MI, STI, OS))
printInstruction(MI, Address, STI, OS);
printAnnotation(OS, Annot);
}
void VEInstPrinter::printOperand(const MCInst *MI, int opNum,
const MCSubtargetInfo &STI, raw_ostream &O) {
const MCOperand &MO = MI->getOperand(opNum);
if (MO.isReg()) {
printRegName(O, MO.getReg());
return;
}
if (MO.isImm()) {
switch (MI->getOpcode()) {
default:
// Expects signed 32bit literals
assert(isInt<32>(MO.getImm()) && "Immediate too large");
int32_t TruncatedImm = static_cast<int32_t>(MO.getImm());
O << TruncatedImm;
return;
}
}
assert(MO.isExpr() && "Unknown operand kind in printOperand");
MO.getExpr()->print(O, &MAI);
}
void VEInstPrinter::printMemASXOperand(const MCInst *MI, int opNum,
const MCSubtargetInfo &STI,
raw_ostream &O, const char *Modifier) {
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
printOperand(MI, opNum, STI, O);
O << ", ";
printOperand(MI, opNum + 1, STI, O);
return;
}
const MCOperand &MO = MI->getOperand(opNum + 1);
if (!MO.isImm() || MO.getImm() != 0) {
printOperand(MI, opNum + 1, STI, O);
}
O << "(,";
printOperand(MI, opNum, STI, O);
O << ")";
}
void VEInstPrinter::printMemASOperand(const MCInst *MI, int opNum,
const MCSubtargetInfo &STI,
raw_ostream &O, const char *Modifier) {
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
printOperand(MI, opNum, STI, O);
O << ", ";
printOperand(MI, opNum + 1, STI, O);
return;
}
const MCOperand &MO = MI->getOperand(opNum + 1);
if (!MO.isImm() || MO.getImm() != 0) {
printOperand(MI, opNum + 1, STI, O);
}
O << "(";
printOperand(MI, opNum, STI, O);
O << ")";
}
void VEInstPrinter::printCCOperand(const MCInst *MI, int opNum,
const MCSubtargetInfo &STI, raw_ostream &O) {
int CC = (int)MI->getOperand(opNum).getImm();
O << VECondCodeToString((VECC::CondCodes)CC);
}