module test;
wire clk;
wire stall;
wire[4:0] in1, out1, out2, out3, out4, out5, out6;
wire stall_1;

assign stall_1 = 0;

Clock clock(clk);
testPC tpc(clk, stall, in1);
testA ta1(clk, stall, in1, out1);
testA ta2(clk, stall, out1, out2);
testA ta3(clk, stall, out2, out3);
testA ta4(clk, stall_1, out3, out4);
testA ta5(clk, stall_1, out4, out5);
testA ta6(clk, stall_1, out5, out6);
testB stl(clk, out1, stall);

initial begin
end
endmodule


module testA(clk, stall, in1, out1);
input clk, stall;
input[4:0] in1;
output reg[4:0] out1;

reg[4:0] temp1;
reg stallfinished;

initial begin
	temp1 = 5'b00000;
	out1 = 5'b00000;
	stallfinished = 1'b0;
end

always @(posedge clk) begin
	if(stall == 1'b1) out1 <= 5'b00000;
	else if(stallfinished == 1'b1) begin
		out1 <= temp1;
		stallfinished <= 1'b0;
	end
	else out1 <= in1;
end
always @(posedge stall) begin
	temp1 = in1;
end
always @(negedge stall) begin
	stallfinished = 1'b1;
end
endmodule


module testB(clk, out1, stall);
input clk;
input[4:0] out1;
output reg stall;

integer i;

initial begin
	stall = 1'b0;
	i = 0;
end

always @(negedge clk)
	if(i > 0) i = i-1;
	else begin
		if(out1 == 5'b00101) begin
			i = 2;
			stall = 1'b1;
		end
		else stall = 1'b0;
	end	
endmodule


module testPC(clk, stall, in1);
input clk, stall;
output reg[4:0] in1;

reg[4:0] PC;

initial begin
	PC = 5'd0;
end
always @(posedge clk) begin
	if(stall == 1'b0) PC <= PC+1;
	in1 <= PC;
end
endmodule

/*
module test;

wire clk;
reg sig1;
reg[31:0] in1;
wire[31:0] out1, out2;

Clock clock(clk);
testA ta(clk, sig1, in1, out1, out2);

initial begin
	sig1 <= 1'b0;
	in1 <= 32'd0;
	#100;
	in1 <= 32'hffffffff;
	#100;
	sig1 <= 1'b1;
	in1 <= 32'h0000ffff; 
	#100;
	sig1 <= 1'b1;
	in1 <= 32'hffff0000; 
	#100;
end

endmodule

module testA(clk, sig1, in1, out1, out2);

input clk, sig1;
input[31:0] in1;
output reg[31:0] out1, out2;

always @(posedge clk) begin
	out1 <= in1;
	if(sig1 == 1) out2 <= in1;
end

endmodule
*/