module IF_ID(clk, in_instruction, in_PC_4, 
	out_instruction, out_PC_4);
input clk;
input[31:0] in_instruction, in_PC_4;
output reg[31:0] out_instruction, out_PC_4;

always @(posedge clk) begin
	out_instruction <= in_instruction;
	out_PC_4 <= in_PC_4;
end
endmodule


module ID_EX(clk, in_writereg_num, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg, 
	in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2, 
	out_writereg_num, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg, 
	out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2);
input clk;
input[4:0] in_writereg_num;
input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg;
input[3:0] in_aluctrl;
input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2;
output reg[4:0] out_writereg_num;
output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg;
output reg[3:0] out_aluctrl;
output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2;

always @(posedge clk) begin
	out_writereg_num <= in_writereg_num;
	out_regwrite <= in_regwrite;
	out_alusrc <= in_alusrc;
	out_aluctrl <= in_aluctrl;
	out_memread <= in_memread;
	out_memwrite <= in_memwrite;
	out_memtoreg <= in_memtoreg;
	out_branch <= in_branch;
	out_jump <= in_jump;
	out_jumpreg <= in_jumpreg;

	out_readdata1 <= in_readdata1;
	out_readdata2 <= in_readdata2;
	out_extenddata <= in_extenddata;
	out_PC_4 <= out_PC_4;
	out_tempPCjump <= in_tempPCjump;
	out_readreg_num1 <= in_readreg_num1;
	out_readreg_num2 <= in_readreg_num2;
end
endmodule


module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, 
	in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch, 
	out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, 
	out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
input clk;
input[4:0] in_writereg_num;
input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
output reg[4:0] out_writereg_num;
output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump;
output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;

always @(posedge clk) begin
	out_writereg_num <= in_writereg_num;
	out_regwrite <= in_regwrite;
	out_memread <= in_memread;
	out_memwrite <= in_memwrite;
	out_memtoreg <= in_memtoreg;
	out_branch <= in_branch;
	out_jump <= in_jump;

	out_aluresult <= in_aluresult;
	out_mem_writedata <= in_mem_writedata;
	out_PC_4 <= in_PC_4;
	out_PCjump <= in_PCjump;
	out_tempPCbranch <= in_tempPCbranch;
end
endmodule


module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump, 
	out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCbranch, out_PCjump);
input clk;
input[4:0] in_writereg_num;
input in_regwrite, in_memtoreg, in_jump;
input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
output reg[4:0] out_writereg_num;
output reg out_regwrite, out_memtoreg, out_jump;
output reg[31:0] out_aluresult, out_memreaddata, out_PCbranch, out_PCjump;

always @(posedge clk) begin
	out_writereg_num <= in_writereg_num;
	out_regwrite <= in_regwrite;
	out_memtoreg <= in_memtoreg;
	out_jump <= in_jump;

	out_aluresult <= in_aluresult;
	out_memreaddata <= in_memreaddata;
	out_PCbranch <= out_PCbranch;
	out_PCjump <= out_PCjump;
end
endmodule

/* Not Finished */
module PCcounter(clk, in_pc, out_nextpc);
input clk;
input[31:0] in_pc;
output reg[31:0] out_nextpc;
reg[31:0] PC;

initial begin
	PC = 32'h00000000;
end

always @(posedge clk) begin
/*
	case(in_pc[31])					// if in_pc is available, PC = in_pc.
		1'b0: PC = in_pc;
		1'b1: PC = in_pc;
	endcase
*/
	PC <= PC+4;
	out_nextpc <= PC;
end

endmodule