module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg, link);
input[5:0] opcode;
input[4:0] rt;
input[5:0] funct;
output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, jump, jumpreg, link;
output reg[3:0] aluctrl;
output reg[2:0] branch;

always @(*) begin
	case(opcode)
		6'b000000: begin		// R type instruction
			regdst = 1'b1;
			regwrite = 1'b1;
			alusrc = 1'b0;
			memread = 1'b0;
			memwrite = 1'b0;
			memtoreg = 1'b0;
			branch = 3'b000;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
			case(funct)
				6'b100000: aluctrl = 4'b0010;	//  add
				6'b100001: aluctrl = 4'b0010;	//  addu
				6'b100010: aluctrl = 4'b0110;	//  sub
				6'b100011: aluctrl = 4'b0110;	//  subu
				6'b100100: aluctrl = 4'b0000;	//  and
				6'b100101: aluctrl = 4'b0001;	//  or
				6'b100110: aluctrl = 4'b1101;	//  xor
				6'b011000: aluctrl = 4'b1000;	//  mult
				6'b011001: aluctrl = 4'b1000;	//  multu
				6'b011010: aluctrl = 4'b1001;	//  div
				6'b011011: aluctrl = 4'b1001;	//  divu
				6'b101010: aluctrl = 4'b0111;	//  slt
				6'b101011: aluctrl = 4'b0111;	//  sltu
				6'b010000: aluctrl = 4'b1010;	//  mfhi
				6'b010010: aluctrl = 4'b1011;	//  mflo
				6'b001000: begin		//  jr
			//		regdst = 1'bz;
					regwrite = 1'b0;
					alusrc = 1'b1;
					aluctrl = 4'b1111;
				//	memread = 1'b0;
				//	memwrite = 1'b0;
			//		memtoreg = 1'bz;
				//	branch = 3'b000;
					jump = 1'b1;
					jumpreg = 1'b1;
				//	link = 1'b0;
				end
				default: begin
			//		regdst = 1'bz;
					regwrite = 1'b0;
					alusrc = 1'b1;
					aluctrl = 4'b1111;
				//	memread = 1'b0;
				//	memwrite = 1'b0;
			//		memtoreg = 1'bz;
				//	branch = 3'b000;
				//	jump = 1'b0;
				//	jumpreg = 1'b0;
				//	link = 1'b0;
				end
			endcase
		end

		6'b001000: begin		// addi instruction
			regdst = 1'b0;
			regwrite = 1'b1;
			alusrc = 1'b1;
			aluctrl = 4'b0010;		// add
			memread = 1'b0;
			memwrite = 1'b0;
			memtoreg = 1'b0;
			branch = 3'b000;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b001001: begin		// addiu instruction
			regdst = 1'b0;
			regwrite = 1'b1;
			alusrc = 1'b1;
			aluctrl = 4'b0010;		// add
			memread = 1'b0;
			memwrite = 1'b0;
			memtoreg = 1'b0;
			branch = 3'b000;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b001100: begin		// andi instruction
			regdst = 1'b0;
			regwrite = 1'b1;
			alusrc = 1'b1;
			aluctrl = 4'b0000;		// and
			memread = 1'b0;
			memwrite = 1'b0;
			memtoreg = 1'b0;
			branch = 3'b000;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b000100: begin		// beq instruction
		//	regdst = 1'bz;
			regwrite = 1'b0;
			alusrc = 1'b0;
			aluctrl = 4'b0110;		// sub
			memread = 1'b0;
			memwrite = 1'b0;
		//	memtoreg = 1'bz;
			branch = 3'b001;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b000101: begin		// bne instruction
		//	regdst = 1'bz;
			regwrite = 1'b0;
			alusrc = 1'b0;
			aluctrl = 4'b0110;		// sub
			memread = 1'b0;
			memwrite = 1'b0;
		//	memtoreg = 1'bz;
			branch = 3'b010;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b000111: begin		// bgtz instruction
		//	regdst = 1'bz;
			regwrite = 1'b0;
			alusrc = 1'b0;
			aluctrl = 4'b0110;		// sub
			memread = 1'b0;
			memwrite = 1'b0;
		//	memtoreg = 1'bz;
			branch = 3'b011;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b000001: begin
			case(rt)
			5'b00000: begin		// bltz instruction
		//		regdst = 1'bz;
				regwrite = 1'b0;
				alusrc = 1'b0;
				aluctrl = 4'b0110;	// sub
				memread = 1'b0;
				memwrite = 1'b0;
		//		memtoreg = 1'bz;
				branch = 3'b100;
				jump = 1'b0;
				jumpreg = 1'b0;
				link = 1'b0;
			end
			5'b00001: begin		// bgez instruction
		//		regdst = 1'bz;
				regwrite = 1'b0;
				alusrc = 1'b0;
				aluctrl = 4'b0110;	// sub
				memread = 1'b0;
				memwrite = 1'b0;
		//		memtoreg = 1'bz;
				branch = 3'b101;
				jump = 1'b0;
				jumpreg = 1'b0;
				link = 1'b0;
			end
			5'b10000: begin		// bltzal instruction
		//		regdst = 1'bz;
				regwrite = 1'b1;
				alusrc = 1'b0;
				aluctrl = 4'b0110;	// sub
				memread = 1'b0;
				memwrite = 1'b0;
		//		memtoreg = 1'bz;
				branch = 3'b100;
				jump = 1'b0;
				jumpreg = 1'b0;
				link = 1'b1;
			end
			5'b10001: begin		// bgezal instruction
		//		regdst = 1'bz;
				regwrite = 1'b1;
				alusrc = 1'b0;
				aluctrl = 4'b0110;	// sub
				memread = 1'b0;
				memwrite = 1'b0;
		//		memtoreg = 1'bz;
				branch = 3'b101;
				jump = 1'b0;
				jumpreg = 1'b0;
				link = 1'b1;
			end
			endcase
		end
		
		6'b000111: begin		// blez instruction
		//	regdst = 1'bz;
			regwrite = 1'b0;
			alusrc = 1'b0;
			aluctrl = 4'b0110;		// sub
			memread = 1'b0;
			memwrite = 1'b0;
		//	memtoreg = 1'bz;
			branch = 3'b110;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b000010: begin		// jump instruction
		//	regdst = 1'bz;
			regwrite = 1'b0;
			alusrc = 1'b1;
			aluctrl = 4'b1111;
			memread = 1'b0;
			memwrite = 1'b0;
		//	memtoreg = 1'bz;
			branch = 3'b000;
			jump = 1'b1;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b000011: begin		// jal instruction
		//	regdst = 1'bz;
			regwrite = 1'b1;
			alusrc = 1'b1;
			aluctrl = 4'b1111;
			memread = 1'b0;
			memwrite = 1'b0;
		//	memtoreg = 1'bz;
			branch = 3'b000;
			jump = 1'b1;
			jumpreg = 1'b0;
			link = 1'b1;
		end

		6'b100011: begin		// lw instruction
			regdst = 1'b0;
			regwrite = 1'b1;
			alusrc = 1'b1;
			aluctrl = 4'b0010;		// add
			memread = 1'b1;
			memwrite = 1'b0;
			memtoreg = 1'b1;
			branch = 3'b000;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		6'b101011: begin		// sw instruction
			regdst = 1'b0;
			regwrite = 1'b0;
			alusrc = 1'b1;
			aluctrl = 4'b0010;		// add
			memread = 1'b0;
			memwrite = 1'b1;
		//	memtoreg = 1'bz;
			branch = 3'b000;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end

		default: begin			// unknown instruction
		//	regdst = 1'bz;
			regwrite = 1'b0;
			alusrc = 1'b1;
			aluctrl = 4'b1111;
			memread = 1'b0;
			memwrite = 1'b0;
		//	memtoreg = 1'bz;
			branch = 3'b000;
			jump = 1'b0;
			jumpreg = 1'b0;
			link = 1'b0;
		end
	endcase
end

endmodule