module DataMemory(clk, address, writedata, memread, memwrite, readdata);
input clk;
input[31:0] address, writedata;
input memread, memwrite;
output reg[31:0] readdata;

integer i;
reg[31:0] mem[255:0];

initial begin
	for(i=0; i<256; i=i+1) mem[i] = 32'd0;
end

always @(negedge clk) begin
	if(memread== 1'b1) begin
		readdata = mem[address/4];
	end
	if(memwrite==1'b1) begin
		mem[address/4] = writedata;
	end
end

endmodule