legalize-intrinsic-round.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP16
# RUN:llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP16
...
---
name: test_f16.round
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $h0
; NO-FP16-LABEL: name: test_f16.round
; NO-FP16: liveins: $h0
; NO-FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT]]
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND]](s32)
; NO-FP16: $h0 = COPY [[FPTRUNC]](s16)
; NO-FP16: RET_ReallyLR implicit $h0
; FP16-LABEL: name: test_f16.round
; FP16: liveins: $h0
; FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s16) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $h0 = COPY [[INTRINSIC_ROUND]](s16)
; FP16: RET_ReallyLR implicit $h0
%0:_(s16) = COPY $h0
%1:_(s16) = G_INTRINSIC_ROUND %0
$h0 = COPY %1(s16)
RET_ReallyLR implicit $h0
...
---
name: test_f32.round
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $s0
; NO-FP16-LABEL: name: test_f32.round
; NO-FP16: liveins: $s0
; NO-FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[COPY]]
; NO-FP16: $s0 = COPY [[INTRINSIC_ROUND]](s32)
; NO-FP16: RET_ReallyLR implicit $s0
; FP16-LABEL: name: test_f32.round
; FP16: liveins: $s0
; FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $s0 = COPY [[INTRINSIC_ROUND]](s32)
; FP16: RET_ReallyLR implicit $s0
%0:_(s32) = COPY $s0
%1:_(s32) = G_INTRINSIC_ROUND %0
$s0 = COPY %1(s32)
RET_ReallyLR implicit $s0
...
---
name: test_f64.round
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0
; NO-FP16-LABEL: name: test_f64.round
; NO-FP16: liveins: $d0
; NO-FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[COPY]]
; NO-FP16: $d0 = COPY [[INTRINSIC_ROUND]](s64)
; NO-FP16: RET_ReallyLR implicit $d0
; FP16-LABEL: name: test_f64.round
; FP16: liveins: $d0
; FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s64) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $d0 = COPY [[INTRINSIC_ROUND]](s64)
; FP16: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0
%1:_(s64) = G_INTRINSIC_ROUND %0
$d0 = COPY %1(s64)
RET_ReallyLR implicit $d0
...
---
name: test_v8f16.round
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0
; NO-FP16-LABEL: name: test_v8f16.round
; NO-FP16: liveins: $q0
; NO-FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT]]
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND]](s32)
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
; NO-FP16: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT1]]
; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND1]](s32)
; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
; NO-FP16: [[INTRINSIC_ROUND2:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT2]]
; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND2]](s32)
; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
; NO-FP16: [[INTRINSIC_ROUND3:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT3]]
; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND3]](s32)
; NO-FP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
; NO-FP16: [[INTRINSIC_ROUND4:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT4]]
; NO-FP16: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND4]](s32)
; NO-FP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
; NO-FP16: [[INTRINSIC_ROUND5:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT5]]
; NO-FP16: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND5]](s32)
; NO-FP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
; NO-FP16: [[INTRINSIC_ROUND6:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT6]]
; NO-FP16: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND6]](s32)
; NO-FP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
; NO-FP16: [[INTRINSIC_ROUND7:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT7]]
; NO-FP16: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND7]](s32)
; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
; NO-FP16: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
; NO-FP16: RET_ReallyLR implicit $q0
; FP16-LABEL: name: test_v8f16.round
; FP16: liveins: $q0
; FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $q0 = COPY [[INTRINSIC_ROUND]](<8 x s16>)
; FP16: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = G_INTRINSIC_ROUND %0
$q0 = COPY %1(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: test_v4f16.round
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0
; NO-FP16-LABEL: name: test_v4f16.round
; NO-FP16: liveins: $d0
; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT]]
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND]](s32)
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
; NO-FP16: [[INTRINSIC_ROUND1:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT1]]
; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND1]](s32)
; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
; NO-FP16: [[INTRINSIC_ROUND2:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT2]]
; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND2]](s32)
; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
; NO-FP16: [[INTRINSIC_ROUND3:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FPEXT3]]
; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[INTRINSIC_ROUND3]](s32)
; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
; NO-FP16: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
; NO-FP16: RET_ReallyLR implicit $d0
; FP16-LABEL: name: test_v4f16.round
; FP16: liveins: $d0
; FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<4 x s16>) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $d0 = COPY [[INTRINSIC_ROUND]](<4 x s16>)
; FP16: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = G_INTRINSIC_ROUND %0
$d0 = COPY %1(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: test_v2f32.round
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0
; NO-FP16-LABEL: name: test_v2f32.round
; NO-FP16: liveins: $d0
; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_ROUND [[COPY]]
; NO-FP16: $d0 = COPY [[INTRINSIC_ROUND]](<2 x s32>)
; NO-FP16: RET_ReallyLR implicit $d0
; FP16-LABEL: name: test_v2f32.round
; FP16: liveins: $d0
; FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $d0 = COPY [[INTRINSIC_ROUND]](<2 x s32>)
; FP16: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = G_INTRINSIC_ROUND %0
$d0 = COPY %1(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: test_v4f32.round
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0
; NO-FP16-LABEL: name: test_v4f32.round
; NO-FP16: liveins: $q0
; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUND [[COPY]]
; NO-FP16: $q0 = COPY [[INTRINSIC_ROUND]](<4 x s32>)
; NO-FP16: RET_ReallyLR implicit $q0
; FP16-LABEL: name: test_v4f32.round
; FP16: liveins: $q0
; FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $q0 = COPY [[INTRINSIC_ROUND]](<4 x s32>)
; FP16: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_INTRINSIC_ROUND %0
$q0 = COPY %1(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f64.round
alignment: 4
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0
; NO-FP16-LABEL: name: test_v2f64.round
; NO-FP16: liveins: $q0
; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; NO-FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUND [[COPY]]
; NO-FP16: $q0 = COPY [[INTRINSIC_ROUND]](<2 x s64>)
; NO-FP16: RET_ReallyLR implicit $q0
; FP16-LABEL: name: test_v2f64.round
; FP16: liveins: $q0
; FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; FP16: [[INTRINSIC_ROUND:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC_ROUND [[COPY]]
; FP16: $q0 = COPY [[INTRINSIC_ROUND]](<2 x s64>)
; FP16: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = G_INTRINSIC_ROUND %0
$q0 = COPY %1(<2 x s64>)
RET_ReallyLR implicit $q0