select-dup.mir
7.13 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.
...
---
name: DUPv4i32gpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; CHECK-LABEL: name: DUPv4i32gpr
; CHECK: liveins: $w0
; CHECK: %copy:gpr32 = COPY $w0
; CHECK: %dup:fpr128 = DUPv4i32gpr %copy
; CHECK: $q0 = COPY %dup
; CHECK: RET_ReallyLR implicit $q0
%copy:gpr(s32) = COPY $w0
%dup:fpr(<4 x s32>) = G_DUP %copy(s32)
$q0 = COPY %dup(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: DUPv2i64gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: DUPv2i64gpr
; CHECK: liveins: $x0
; CHECK: %copy:gpr64 = COPY $x0
; CHECK: %dup:fpr128 = DUPv2i64gpr %copy
; CHECK: $q0 = COPY %dup
; CHECK: RET_ReallyLR implicit $q0
%copy:gpr(s64) = COPY $x0
%dup:fpr(<2 x s64>) = G_DUP %copy(s64)
$q0 = COPY %dup(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: DUPv2i32gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; CHECK-LABEL: name: DUPv2i32gpr
; CHECK: liveins: $w0
; CHECK: %copy:gpr32 = COPY $w0
; CHECK: %dup:fpr64 = DUPv2i32gpr %copy
; CHECK: $d0 = COPY %dup
; CHECK: RET_ReallyLR implicit $d0
%copy:gpr(s32) = COPY $w0
%dup:fpr(<2 x s32>) = G_DUP %copy(s32)
$d0 = COPY %dup(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: DUPv4i32lane
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $s0
; CHECK-LABEL: name: DUPv4i32lane
; CHECK: liveins: $s0
; CHECK: %copy:fpr32 = COPY $s0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
; CHECK: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
; CHECK: $q0 = COPY %dup
; CHECK: RET_ReallyLR implicit $q0
%copy:fpr(s32) = COPY $s0
%dup:fpr(<4 x s32>) = G_DUP %copy(s32)
$q0 = COPY %dup(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: DUPv2i64lane
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: DUPv2i64lane
; CHECK: liveins: $d0
; CHECK: %copy:fpr64 = COPY $d0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.dsub
; CHECK: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
; CHECK: $q0 = COPY %dup
; CHECK: RET_ReallyLR implicit $q0
%copy:fpr(s64) = COPY $d0
%dup:fpr(<2 x s64>) = G_DUP %copy(s64)
$q0 = COPY %dup(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: DUPv2i32lane
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $s0
; CHECK-LABEL: name: DUPv2i32lane
; CHECK: liveins: $s0
; CHECK: %copy:fpr32 = COPY $s0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
; CHECK: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
; CHECK: $d0 = COPY %dup
; CHECK: RET_ReallyLR implicit $d0
%copy:fpr(s32) = COPY $s0
%dup:fpr(<2 x s32>) = G_DUP %copy(s32)
$d0 = COPY %dup(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: DUPv4i16lane
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $h0
; CHECK-LABEL: name: DUPv4i16lane
; CHECK: liveins: $h0
; CHECK: %copy:fpr16 = COPY $h0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
; CHECK: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
; CHECK: $d0 = COPY %dup
; CHECK: RET_ReallyLR implicit $d0
%copy:fpr(s16) = COPY $h0
%dup:fpr(<4 x s16>) = G_DUP %copy(s16)
$d0 = COPY %dup(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: DUPv4i16gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; CHECK-LABEL: name: DUPv4i16gpr
; CHECK: liveins: $w0
; CHECK: %copy:gpr32 = COPY $w0
; CHECK: %dup:fpr64 = DUPv4i16gpr %copy
; CHECK: $d0 = COPY %dup
; CHECK: RET_ReallyLR implicit $d0
%copy:gpr(s32) = COPY $w0
%dup:fpr(<4 x s16>) = G_DUP %copy(s32)
$d0 = COPY %dup(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: DUPv8i16lane
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $h0
; CHECK-LABEL: name: DUPv8i16lane
; CHECK: liveins: $h0
; CHECK: %copy:fpr16 = COPY $h0
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
; CHECK: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
; CHECK: $q0 = COPY %dup
; CHECK: RET_ReallyLR implicit $q0
%copy:fpr(s16) = COPY $h0
%dup:fpr(<8 x s16>) = G_DUP %copy(s16)
$q0 = COPY %dup(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: DUPv8i16gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; CHECK-LABEL: name: DUPv8i16gpr
; CHECK: liveins: $w0
; CHECK: %copy:gpr32 = COPY $w0
; CHECK: %dup:fpr128 = DUPv8i16gpr %copy
; CHECK: $q0 = COPY %dup
; CHECK: RET_ReallyLR implicit $q0
%copy:gpr(s32) = COPY $w0
%dup:fpr(<8 x s16>) = G_DUP %copy(s32)
$q0 = COPY %dup(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: DUPv8i8gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; CHECK-LABEL: name: DUPv8i8gpr
; CHECK: liveins: $w0
; CHECK: %copy:gpr32 = COPY $w0
; CHECK: %dup:fpr64 = DUPv8i8gpr %copy
; CHECK: $d0 = COPY %dup
; CHECK: RET_ReallyLR implicit $d0
%copy:gpr(s32) = COPY $w0
%dup:fpr(<8 x s8>) = G_DUP %copy(s32)
$d0 = COPY %dup(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: DUPv16i8gpr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; CHECK-LABEL: name: DUPv16i8gpr
; CHECK: liveins: $w0
; CHECK: %copy:gpr32 = COPY $w0
; CHECK: %dup:fpr128 = DUPv16i8gpr %copy
; CHECK: $q0 = COPY %dup
; CHECK: RET_ReallyLR implicit $q0
%copy:gpr(s32) = COPY $w0
%dup:fpr(<16 x s8>) = G_DUP %copy(s32)
$q0 = COPY %dup(<16 x s8>)
RET_ReallyLR implicit $q0