select-trn.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that we can select G_TRN1 and G_TRN2.
#
# Each testcase is named based off of the instruction which should be selected.
...
---
name: TRN1v2i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: TRN1v2i32
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[TRN1v2i32_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s32>) = COPY $d1
%2:fpr(<2 x s32>) = G_TRN1 %0, %1
$d0 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: TRN1v2i64
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN1v2i64
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN1v2i64_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s64>) = COPY $q1
%2:fpr(<2 x s64>) = G_TRN1 %0, %1
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: TRN1v4i16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: TRN1v4i16
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[TRN1v4i16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_TRN1 %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: TRN1v4i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN1v4i32
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN1v4i32_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = G_TRN1 %0, %1
$q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: TRN1v8i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: TRN1v8i8
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[TRN1v8i8_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s8>) = COPY $d1
%2:fpr(<8 x s8>) = G_TRN1 %0, %1
$d0 = COPY %2(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: TRN1v8i16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN1v8i16
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN1v8i16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = COPY $q1
%2:fpr(<8 x s16>) = G_TRN1 %0, %1
$q0 = COPY %2(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: TRN1v16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN1v16i8
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN1v16i8_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<16 x s8>) = COPY $q0
%1:fpr(<16 x s8>) = COPY $q1
%2:fpr(<16 x s8>) = G_TRN1 %0, %1
$q0 = COPY %2(<16 x s8>)
RET_ReallyLR implicit $q0
...
---
name: TRN2v2i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: TRN2v2i32
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[TRN2v2i32_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s32>) = COPY $d1
%2:fpr(<2 x s32>) = G_TRN2 %0, %1
$d0 = COPY %2(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: TRN2v2i64
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN2v2i64
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN2v2i64_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s64>) = COPY $q1
%2:fpr(<2 x s64>) = G_TRN2 %0, %1
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: TRN2v4i16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: TRN2v4i16
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[TRN2v4i16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = G_TRN2 %0, %1
$d0 = COPY %2(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: TRN2v4i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN2v4i32
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN2v4i32_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = G_TRN2 %0, %1
$q0 = COPY %2(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: TRN2v8i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: TRN2v8i8
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[TRN2v8i8_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s8>) = COPY $d1
%2:fpr(<8 x s8>) = G_TRN2 %0, %1
$d0 = COPY %2(<8 x s8>)
RET_ReallyLR implicit $d0
...
---
name: TRN2v8i16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN2v8i16
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN2v8i16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = COPY $q1
%2:fpr(<8 x s16>) = G_TRN2 %0, %1
$q0 = COPY %2(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: TRN2v16i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: TRN2v16i8
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]
; CHECK: $q0 = COPY [[TRN2v16i8_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<16 x s8>) = COPY $q0
%1:fpr(<16 x s8>) = COPY $q1
%2:fpr(<16 x s8>) = G_TRN2 %0, %1
$q0 = COPY %2(<16 x s8>)
RET_ReallyLR implicit $q0