rotate-extract.ll
4.08 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
; Check that under certain conditions we can factor out a rotate
; from the following idioms:
; (a*c0) >> s1 | (a*c1)
; (a/c0) << s1 | (a/c1)
; This targets cases where instcombine has folded a shl/srl/mul/udiv
; with one of the shifts from the rotate idiom
define i64 @ror_extract_shl(i64 %i) nounwind {
; CHECK-LABEL: ror_extract_shl:
; CHECK: // %bb.0:
; CHECK-NEXT: lsl x8, x0, #3
; CHECK-NEXT: ror x0, x8, #57
; CHECK-NEXT: ret
%lhs_mul = shl i64 %i, 3
%rhs_mul = shl i64 %i, 10
%lhs_shift = lshr i64 %lhs_mul, 57
%out = or i64 %lhs_shift, %rhs_mul
ret i64 %out
}
define i32 @ror_extract_shrl(i32 %i) nounwind {
; CHECK-LABEL: ror_extract_shrl:
; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, #3
; CHECK-NEXT: ror w0, w8, #4
; CHECK-NEXT: ret
%lhs_div = lshr i32 %i, 7
%rhs_div = lshr i32 %i, 3
%rhs_shift = shl i32 %rhs_div, 28
%out = or i32 %lhs_div, %rhs_shift
ret i32 %out
}
define i32 @ror_extract_mul(i32 %i) nounwind {
; CHECK-LABEL: ror_extract_mul:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w0, lsl #3
; CHECK-NEXT: ror w0, w8, #25
; CHECK-NEXT: ret
%lhs_mul = mul i32 %i, 9
%rhs_mul = mul i32 %i, 1152
%lhs_shift = lshr i32 %lhs_mul, 25
%out = or i32 %lhs_shift, %rhs_mul
ret i32 %out
}
define i64 @ror_extract_udiv(i64 %i) nounwind {
; CHECK-LABEL: ror_extract_udiv:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-6148914691236517206
; CHECK-NEXT: movk x8, #43691
; CHECK-NEXT: umulh x8, x0, x8
; CHECK-NEXT: lsr x8, x8, #1
; CHECK-NEXT: ror x0, x8, #4
; CHECK-NEXT: ret
%lhs_div = udiv i64 %i, 3
%rhs_div = udiv i64 %i, 48
%lhs_shift = shl i64 %lhs_div, 60
%out = or i64 %lhs_shift, %rhs_div
ret i64 %out
}
define i64 @ror_extract_mul_with_mask(i64 %i) nounwind {
; CHECK-LABEL: ror_extract_mul_with_mask:
; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, x0, lsl #3
; CHECK-NEXT: ror x8, x8, #57
; CHECK-NEXT: and x0, x8, #0xff
; CHECK-NEXT: ret
%lhs_mul = mul i64 %i, 1152
%rhs_mul = mul i64 %i, 9
%lhs_and = and i64 %lhs_mul, 160
%rhs_shift = lshr i64 %rhs_mul, 57
%out = or i64 %lhs_and, %rhs_shift
ret i64 %out
}
; Result would undershift
define i64 @no_extract_shl(i64 %i) nounwind {
; CHECK-LABEL: no_extract_shl:
; CHECK: // %bb.0:
; CHECK-NEXT: lsl x8, x0, #10
; CHECK-NEXT: bfxil x8, x0, #52, #7
; CHECK-NEXT: mov x0, x8
; CHECK-NEXT: ret
%lhs_mul = shl i64 %i, 5
%rhs_mul = shl i64 %i, 10
%lhs_shift = lshr i64 %lhs_mul, 57
%out = or i64 %lhs_shift, %rhs_mul
ret i64 %out
}
; Result would overshift
define i32 @no_extract_shrl(i32 %i) nounwind {
; CHECK-LABEL: no_extract_shrl:
; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, #3
; CHECK-NEXT: lsr w0, w0, #9
; CHECK-NEXT: bfi w0, w8, #28, #4
; CHECK-NEXT: ret
%lhs_div = lshr i32 %i, 3
%rhs_div = lshr i32 %i, 9
%lhs_shift = shl i32 %lhs_div, 28
%out = or i32 %lhs_shift, %rhs_div
ret i32 %out
}
; Can factor 128 from 2304, but result is 18 instead of 9
define i64 @no_extract_mul(i64 %i) nounwind {
; CHECK-LABEL: no_extract_mul:
; CHECK: // %bb.0:
; CHECK-NEXT: add x8, x0, x0, lsl #3
; CHECK-NEXT: lsr x0, x8, #57
; CHECK-NEXT: bfi x0, x8, #8, #56
; CHECK-NEXT: ret
%lhs_mul = mul i64 %i, 2304
%rhs_mul = mul i64 %i, 9
%rhs_shift = lshr i64 %rhs_mul, 57
%out = or i64 %lhs_mul, %rhs_shift
ret i64 %out
}
; Can't evenly factor 16 from 49
define i32 @no_extract_udiv(i32 %i) nounwind {
; CHECK-LABEL: no_extract_udiv:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43691
; CHECK-NEXT: mov w9, #33437
; CHECK-NEXT: movk w8, #43690, lsl #16
; CHECK-NEXT: movk w9, #21399, lsl #16
; CHECK-NEXT: umull x8, w0, w8
; CHECK-NEXT: umull x9, w0, w9
; CHECK-NEXT: lsr x8, x8, #33
; CHECK-NEXT: lsr x9, x9, #32
; CHECK-NEXT: extr w0, w8, w9, #4
; CHECK-NEXT: ret
%lhs_div = udiv i32 %i, 3
%rhs_div = udiv i32 %i, 49
%lhs_shift = shl i32 %lhs_div, 28
%out = or i32 %lhs_shift, %rhs_div
ret i32 %out
}