int-ssub-05.ll
5.3 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
; Test subtractions between an i64 and a sign-extended i16 on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
declare i64 @foo()
; Check SGH with no displacement.
define zeroext i1 @f1(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f1:
; CHECK: sgh %r3, 0(%r4)
; CHECK-DAG: stg %r3, 0(%r5)
; CHECK-DAG: lghi %r2, 0
; CHECK-DAG: locghio %r2, 1
; CHECK: br %r14
%half = load i16, i16 *%src
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
ret i1 %obit
}
; Check the high end of the aligned SGH range.
define zeroext i1 @f4(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f4:
; CHECK: sgh %r3, 524286(%r4)
; CHECK-DAG: stg %r3, 0(%r5)
; CHECK-DAG: lghi %r2, 0
; CHECK-DAG: locghio %r2, 1
; CHECK: br %r14
%ptr = getelementptr i16, i16 *%src, i64 262143
%half = load i16, i16 *%ptr
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
ret i1 %obit
}
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define zeroext i1 @f5(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f5:
; CHECK: agfi %r4, 524288
; CHECK: sgh %r3, 0(%r4)
; CHECK-DAG: stg %r3, 0(%r5)
; CHECK-DAG: lghi %r2, 0
; CHECK-DAG: locghio %r2, 1
; CHECK: br %r14
%ptr = getelementptr i16, i16 *%src, i64 262144
%half = load i16, i16 *%ptr
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
ret i1 %obit
}
; Check the high end of the negative aligned SGH range.
define zeroext i1 @f6(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f6:
; CHECK: sgh %r3, -2(%r4)
; CHECK-DAG: stg %r3, 0(%r5)
; CHECK-DAG: lghi %r2, 0
; CHECK-DAG: locghio %r2, 1
; CHECK: br %r14
%ptr = getelementptr i16, i16 *%src, i64 -1
%half = load i16, i16 *%ptr
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
ret i1 %obit
}
; Check the low end of the SGH range.
define zeroext i1 @f7(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f7:
; CHECK: sgh %r3, -524288(%r4)
; CHECK-DAG: stg %r3, 0(%r5)
; CHECK-DAG: lghi %r2, 0
; CHECK-DAG: locghio %r2, 1
; CHECK: br %r14
%ptr = getelementptr i16, i16 *%src, i64 -262144
%half = load i16, i16 *%ptr
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
ret i1 %obit
}
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define zeroext i1 @f8(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f8:
; CHECK: agfi %r4, -524290
; CHECK: sgh %r3, 0(%r4)
; CHECK-DAG: stg %r3, 0(%r5)
; CHECK-DAG: lghi %r2, 0
; CHECK-DAG: locghio %r2, 1
; CHECK: br %r14
%ptr = getelementptr i16, i16 *%src, i64 -262145
%half = load i16, i16 *%ptr
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
ret i1 %obit
}
; Check that SGH allows an index.
define zeroext i1 @f9(i64 %src, i64 %index, i64 %a, i64 *%res) {
; CHECK-LABEL: f9:
; CHECK: sgh %r4, 524284({{%r3,%r2|%r2,%r3}})
; CHECK-DAG: stg %r4, 0(%r5)
; CHECK-DAG: lghi %r2, 0
; CHECK-DAG: locghio %r2, 1
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524284
%ptr = inttoptr i64 %add2 to i16 *
%half = load i16, i16 *%ptr
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
ret i1 %obit
}
; Check using the overflow result for a branch.
define void @f11(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f11:
; CHECK: sgh %r3, 0(%r4)
; CHECK: stg %r3, 0(%r5)
; CHECK: jgo foo@PLT
; CHECK: br %r14
%half = load i16, i16 *%src
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
br i1 %obit, label %call, label %exit
call:
tail call i64 @foo()
br label %exit
exit:
ret void
}
; ... and the same with the inverted direction.
define void @f12(i64 %dummy, i64 %a, i16 *%src, i64 *%res) {
; CHECK-LABEL: f12:
; CHECK: sgh %r3, 0(%r4)
; CHECK: stg %r3, 0(%r5)
; CHECK: jgno foo@PLT
; CHECK: br %r14
%half = load i16, i16 *%src
%b = sext i16 %half to i64
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64 *%res
br i1 %obit, label %exit, label %call
call:
tail call i64 @foo()
br label %exit
exit:
ret void
}
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone