mve-vaddv.ll
5.36 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
declare i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64>)
declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32>)
declare i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32>)
declare i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16>)
declare i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16>)
declare i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8>)
declare i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8>)
define arm_aapcs_vfpcc i64 @vaddv_v2i64_i64(<2 x i64> %s1) {
; CHECK-LABEL: vaddv_v2i64_i64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: adds r0, r0, r3
; CHECK-NEXT: adcs r1, r2
; CHECK-NEXT: bx lr
entry:
%r = call i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
ret i64 %r
}
define arm_aapcs_vfpcc i32 @vaddv_v4i32_i32(<4 x i32> %s1) {
; CHECK-LABEL: vaddv_v4i32_i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%r = call i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
ret i32 %r
}
define arm_aapcs_vfpcc i32 @vaddv_v8i32_i32(<8 x i32> %s1) {
; CHECK-LABEL: vaddv_v8i32_i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vaddv.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%r = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
ret i32 %r
}
define arm_aapcs_vfpcc i16 @vaddv_v8i16_i16(<8 x i16> %s1) {
; CHECK-LABEL: vaddv_v8i16_i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: bx lr
entry:
%r = call i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
ret i16 %r
}
define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<16 x i16> %s1) {
; CHECK-LABEL: vaddv_v16i16_i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vaddv.u16 r0, q0
; CHECK-NEXT: bx lr
entry:
%r = call i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
ret i16 %r
}
define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) {
; CHECK-LABEL: vaddv_v16i8_i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddv.u8 r0, q0
; CHECK-NEXT: bx lr
entry:
%r = call i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
ret i8 %r
}
define arm_aapcs_vfpcc i8 @vaddv_v32i8_i8(<32 x i8> %s1) {
; CHECK-LABEL: vaddv_v32i8_i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i8 q0, q0, q1
; CHECK-NEXT: vaddv.u8 r0, q0
; CHECK-NEXT: bx lr
entry:
%r = call i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
ret i8 %r
}
define arm_aapcs_vfpcc i64 @vaddva_v2i64_i64(<2 x i64> %s1, i64 %x) {
; CHECK-LABEL: vaddva_v2i64_i64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r12, s3
; CHECK-NEXT: vmov lr, s1
; CHECK-NEXT: adds r2, r2, r3
; CHECK-NEXT: adc.w r3, lr, r12
; CHECK-NEXT: adds r0, r0, r2
; CHECK-NEXT: adcs r1, r3
; CHECK-NEXT: pop {r7, pc}
entry:
%t = call i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64> %s1)
%r = add i64 %t, %x
ret i64 %r
}
define arm_aapcs_vfpcc i32 @vaddva_v4i32_i32(<4 x i32> %s1, i32 %x) {
; CHECK-LABEL: vaddva_v4i32_i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%t = call i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
%r = add i32 %t, %x
ret i32 %r
}
define arm_aapcs_vfpcc i32 @vaddva_v8i32_i32(<8 x i32> %s1, i32 %x) {
; CHECK-LABEL: vaddva_v8i32_i32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vaddva.u32 r0, q0
; CHECK-NEXT: bx lr
entry:
%t = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %s1)
%r = add i32 %t, %x
ret i32 %r
}
define arm_aapcs_vfpcc i16 @vaddva_v8i16_i16(<8 x i16> %s1, i16 %x) {
; CHECK-LABEL: vaddva_v8i16_i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: bx lr
entry:
%t = call i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
%r = add i16 %t, %x
ret i16 %r
}
define arm_aapcs_vfpcc i16 @vaddva_v16i16_i16(<16 x i16> %s1, i16 %x) {
; CHECK-LABEL: vaddva_v16i16_i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vaddva.u16 r0, q0
; CHECK-NEXT: bx lr
entry:
%t = call i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
%r = add i16 %t, %x
ret i16 %r
}
define arm_aapcs_vfpcc i8 @vaddva_v16i8_i8(<16 x i8> %s1, i8 %x) {
; CHECK-LABEL: vaddva_v16i8_i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vaddva.u8 r0, q0
; CHECK-NEXT: bx lr
entry:
%t = call i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
%r = add i8 %t, %x
ret i8 %r
}
define arm_aapcs_vfpcc i8 @vaddva_v32i8_i8(<32 x i8> %s1, i8 %x) {
; CHECK-LABEL: vaddva_v32i8_i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i8 q0, q0, q1
; CHECK-NEXT: vaddva.u8 r0, q0
; CHECK-NEXT: bx lr
entry:
%t = call i8 @llvm.experimental.vector.reduce.add.i8.v32i8(<32 x i8> %s1)
%r = add i8 %t, %x
ret i8 %r
}