basictest.ll
6.98 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
; RUN: opt < %s -loop-unswitch -enable-new-pm=0 -verify-loop-info -S < %s 2>&1 | FileCheck %s
; RUN: opt < %s -loop-unswitch -enable-new-pm=0 -verify-loop-info -enable-mssa-loop-dependency=true -verify-memoryssa -S < %s 2>&1 | FileCheck %s
define i32 @test(i32* %A, i1 %C) {
entry:
br label %no_exit
no_exit: ; preds = %no_exit.backedge, %entry
%i.0.0 = phi i32 [ 0, %entry ], [ %i.0.0.be, %no_exit.backedge ] ; <i32> [#uses=3]
%gep.upgrd.1 = zext i32 %i.0.0 to i64 ; <i64> [#uses=1]
%tmp.7 = getelementptr i32, i32* %A, i64 %gep.upgrd.1 ; <i32*> [#uses=4]
%tmp.13 = load i32, i32* %tmp.7 ; <i32> [#uses=2]
%tmp.14 = add i32 %tmp.13, 1 ; <i32> [#uses=1]
store i32 %tmp.14, i32* %tmp.7
br i1 %C, label %then, label %endif
then: ; preds = %no_exit
%tmp.29 = load i32, i32* %tmp.7 ; <i32> [#uses=1]
%tmp.30 = add i32 %tmp.29, 2 ; <i32> [#uses=1]
store i32 %tmp.30, i32* %tmp.7
%inc9 = add i32 %i.0.0, 1 ; <i32> [#uses=2]
%tmp.112 = icmp ult i32 %inc9, 100000 ; <i1> [#uses=1]
br i1 %tmp.112, label %no_exit.backedge, label %return
no_exit.backedge: ; preds = %endif, %then
%i.0.0.be = phi i32 [ %inc9, %then ], [ %inc, %endif ] ; <i32> [#uses=1]
br label %no_exit
endif: ; preds = %no_exit
%inc = add i32 %i.0.0, 1 ; <i32> [#uses=2]
%tmp.1 = icmp ult i32 %inc, 100000 ; <i1> [#uses=1]
br i1 %tmp.1, label %no_exit.backedge, label %return
return: ; preds = %endif, %then
ret i32 %tmp.13
}
; This simple test would normally unswitch, but should be inhibited by the presence of
; the noduplicate call.
; CHECK-LABEL: @test2(
define i32 @test2(i32* %var) {
%mem = alloca i32
store i32 2, i32* %mem
%c = load i32, i32* %mem
br label %loop_begin
loop_begin:
%var_val = load i32, i32* %var
switch i32 %c, label %default [
i32 1, label %inc
i32 2, label %dec
]
inc:
call void @incf() noreturn nounwind
br label %loop_begin
dec:
; CHECK: call void @decf()
; CHECK-NOT: call void @decf()
call void @decf() noreturn nounwind noduplicate
br label %loop_begin
default:
br label %loop_exit
loop_exit:
ret i32 0
; CHECK: }
}
; This simple test would normally unswitch, but should be inhibited by the presence of
; the convergent call that is not control-dependent on the unswitch condition.
; CHECK-LABEL: @test3(
define i32 @test3(i32* %var) {
%mem = alloca i32
store i32 2, i32* %mem
%c = load i32, i32* %mem
br label %loop_begin
loop_begin:
%var_val = load i32, i32* %var
; CHECK: call void @conv()
; CHECK-NOT: call void @conv()
call void @conv() convergent
switch i32 %c, label %default [
i32 1, label %inc
i32 2, label %dec
]
inc:
call void @incf() noreturn nounwind
br label %loop_begin
dec:
call void @decf() noreturn nounwind
br label %loop_begin
default:
br label %loop_exit
loop_exit:
ret i32 0
; CHECK: }
}
; Make sure we unswitch %a == 0 out of the loop.
;
; CHECK: define void @and_i2_as_switch_input(i2
; CHECK: entry:
; This is an indication that the loop has been unswitched.
; CHECK: icmp eq i2 %a, 0
; CHECK: br
; There should be no more unswitching after the 1st unswitch.
; CHECK-NOT: icmp eq
; CHECK: ret
define void @and_i2_as_switch_input(i2 %a) {
entry:
br label %for.body
for.body:
%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
%and = and i2 %a, %i
%and1 = and i2 %and, %i
switch i2 %and1, label %sw.default [
i2 0, label %sw.bb
i2 1, label %sw.bb1
]
sw.bb:
br label %sw.epilog
sw.bb1:
br label %sw.epilog
sw.default:
br label %sw.epilog
sw.epilog:
br label %for.inc
for.inc:
%inc = add nsw i2 %i, 1
%cmp = icmp slt i2 %inc, 3
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
; Make sure we unswitch %a == !0 out of the loop.
;
; CHECK: define void @or_i2_as_switch_input(i2
; CHECK: entry:
; This is an indication that the loop has been unswitched.
; CHECK: icmp eq i2 %a, -1
; CHECK: br
; There should be no more unswitching after the 1st unswitch.
; CHECK-NOT: icmp eq
; CHECK: ret
define void @or_i2_as_switch_input(i2 %a) {
entry:
br label %for.body
for.body:
%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
%or = or i2 %a, %i
%or1 = or i2 %or, %i
switch i2 %or1, label %sw.default [
i2 2, label %sw.bb
i2 3, label %sw.bb1
]
sw.bb:
br label %sw.epilog
sw.bb1:
br label %sw.epilog
sw.default:
br label %sw.epilog
sw.epilog:
br label %for.inc
for.inc:
%inc = add nsw i2 %i, 1
%cmp = icmp slt i2 %inc, 3
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
; Make sure we unswitch %a == !0 out of the loop. Even we do not
; have it as a case value. Unswitching it out allows us to simplify
; the or operator chain.
;
; CHECK: define void @or_i2_as_switch_input_unswitch_default(i2
; CHECK: entry:
; This is an indication that the loop has been unswitched.
; CHECK: icmp eq i2 %a, -1
; CHECK: br
; There should be no more unswitching after the 1st unswitch.
; CHECK-NOT: icmp eq
; CHECK: ret
define void @or_i2_as_switch_input_unswitch_default(i2 %a) {
entry:
br label %for.body
for.body:
%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
%or = or i2 %a, %i
%or1 = or i2 %or, %i
switch i2 %or1, label %sw.default [
i2 1, label %sw.bb
i2 2, label %sw.bb1
]
sw.bb:
br label %sw.epilog
sw.bb1:
br label %sw.epilog
sw.default:
br label %sw.epilog
sw.epilog:
br label %for.inc
for.inc:
%inc = add nsw i2 %i, 1
%cmp = icmp slt i2 %inc, 3
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
; Make sure we don't unswitch, as we can not find an input value %a
; that will effectively unswitch 0 or 3 out of the loop.
;
; CHECK: define void @and_or_i2_as_switch_input(i2
; CHECK: entry:
; This is an indication that the loop has NOT been unswitched.
; CHECK-NOT: icmp
; CHECK: br
define void @and_or_i2_as_switch_input(i2 %a) {
entry:
br label %for.body
for.body:
%i = phi i2 [ 0, %entry ], [ %inc, %for.inc ]
%and = and i2 %a, %i
%or = or i2 %and, %i
switch i2 %or, label %sw.default [
i2 0, label %sw.bb
i2 3, label %sw.bb1
]
sw.bb:
br label %sw.epilog
sw.bb1:
br label %sw.epilog
sw.default:
br label %sw.epilog
sw.epilog:
br label %for.inc
for.inc:
%inc = add nsw i2 %i, 1
%cmp = icmp slt i2 %inc, 3
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
; Make sure we don't unswitch, as we can not find an input value %a
; that will effectively unswitch true/false out of the loop.
;
; CHECK: define void @and_or_i1_as_branch_input(i1
; CHECK: entry:
; This is an indication that the loop has NOT been unswitched.
; CHECK-NOT: icmp
; CHECK: br
define void @and_or_i1_as_branch_input(i1 %a) {
entry:
br label %for.body
for.body:
%i = phi i1 [ 0, %entry ], [ %inc, %for.inc ]
%and = and i1 %a, %i
%or = or i1 %and, %i
br i1 %or, label %sw.bb, label %sw.bb1
sw.bb:
br label %sw.epilog
sw.bb1:
br label %sw.epilog
sw.epilog:
br label %for.inc
for.inc:
%inc = add nsw i1 %i, 1
%cmp = icmp slt i1 %inc, 1
br i1 %cmp, label %for.body, label %for.end
for.end:
ret void
}
declare void @incf() noreturn
declare void @decf() noreturn
declare void @conv() convergent