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샘플 명령어 세트 추가, 발표 ppt 자료 추가 및 최종 보고서 제출

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Showing 15 changed files with 166 additions and 485 deletions
......@@ -5,6 +5,7 @@ output reg[31:0] instruction;
reg[31:0] instr_mem[127:0];
/*
// Factorial #1
initial begin
instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
......@@ -15,6 +16,7 @@ instr_mem[4] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[5] = 32'b00010101000010011111111111111100; // bne, $t0($8), $t1($9), -4
instr_mem[6] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2), +0
end
*/
/*
// Factorial #2
......@@ -54,6 +56,40 @@ instr_mem[31] = 32'b00100010000000100000000000000000; // addi, $s0($16), $v0($2
end
*/
// No Hazard
initial begin
instr_mem[0] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
instr_mem[1] = 32'b00100000000010000000000000000001; // addi, $0, $t0($8), +1
instr_mem[2] = 32'b00100000000010010000000000000010; // addi, $0, $t1($9), +2
instr_mem[3] = 32'b00100000000010100000000000000011; // addi, $0, $t2($10), +3
instr_mem[4] = 32'b00100000000010110000000000000100; // addi, $0, $t3($11), +4
instr_mem[5] = 32'b00100000000011000000000000000101; // addi, $0, $t4($12), +5
instr_mem[6] = 32'b00100000000011010000000000000110; // addi, $0, $t5($13), +6
instr_mem[7] = 32'b00000001000010000000000000011000; // mult, $t0($08), $t0($8)
instr_mem[8] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[9] = 32'b00000001000010010000000000011000; // mult, $t0($08), $t1($9)
instr_mem[10] = 32'b00000000000000001000100000010010; // mflo, $s1($17)
instr_mem[11] = 32'b00000001001010010000000000011000; // mult, $t1($9), $t1($9)
instr_mem[12] = 32'b00000000000000001001000000010010; // mflo, $s2($18)
instr_mem[13] = 32'b00000000000000001001100000010010; // mflo, $s3($19)
instr_mem[14] = 32'b00100000000000100000000000011000; // addi, $0, $v0($2), +24
instr_mem[15] = 32'b00100000000100000000000000000001; // addi, $0, $s0($16), +1
instr_mem[16] = 32'b00100000000010000000000000000001; // addi, $0, $t0($8), +1
instr_mem[17] = 32'b00100000000010010000000000000010; // addi, $0, $t1($9), +2
instr_mem[18] = 32'b00100000000010100000000000000011; // addi, $0, $t2($10), +3
instr_mem[19] = 32'b00100000000010110000000000000100; // addi, $0, $t3($11), +4
instr_mem[20] = 32'b00100000000011000000000000000101; // addi, $0, $t4($12), +5
instr_mem[21] = 32'b00100000000011010000000000000110; // addi, $0, $t5($13), +6
instr_mem[22] = 32'b00000001000010000000000000011000; // mult, $t0($08), $t0($8)
instr_mem[23] = 32'b00000000000000001000000000010010; // mflo, $s0($16)
instr_mem[24] = 32'b00000001000010010000000000011000; // mult, $t0($08), $t1($9)
instr_mem[25] = 32'b00000000000000001000100000010010; // mflo, $s1($17)
instr_mem[26] = 32'b00000001001010010000000000011000; // mult, $t1($9), $t1($9)
instr_mem[27] = 32'b00000000000000001001000000010010; // mflo, $s2($18)
instr_mem[28] = 32'b00000000000000001001100000010010; // mflo, $s3($19)
instr_mem[29] = 32'b00100000000000100000000000111000; // addi, $0, $v0($2), +56
end
always @ (*) begin
instruction = instr_mem[address/4];
end
......
D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module MIPS_Pipeline_Forwarding
-- Compiling module Adder
Top level modules:
MIPS_Pipeline_Forwarding
Adder
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Adder
-- Compiling module MIPS_Pipeline_Forwarding
Top level modules:
Adder
MIPS_Pipeline_Forwarding
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
......@@ -33,13 +33,6 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
Top level modules:
Register
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module MIPS_Pipeline
Top level modules:
MIPS_Pipeline
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module PCregister
......@@ -55,6 +48,13 @@ Top level modules:
EX_MEM
MEM_WB
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module MIPS_Pipeline
Top level modules:
MIPS_Pipeline
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module HazardHandling
......@@ -66,6 +66,13 @@ Top level modules:
HazardHandling_Forwarding
Mux_Forwarding
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module SignExtend
Top level modules:
SignExtend
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Control
......@@ -73,12 +80,12 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
Top level modules:
Control
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module SignExtend
-- Compiling module ALU
Top level modules:
SignExtend
ALU
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
......@@ -91,12 +98,12 @@ Top level modules:
Mux32bit
MuxBranchSignal
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ALU
-- Compiling module ShiftLeft2
Top level modules:
ALU
ShiftLeft2
} {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
......@@ -105,14 +112,7 @@ Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7
Top level modules:
DataMemory
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module ShiftLeft2
Top level modules:
ShiftLeft2
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
-- Compiling module Clock
-- Compiling module Clock_pipeline
......
This diff is collapsed. Click to expand it.
module test;
wire clk;
wire stall;
wire[4:0] in1, out1, out2, out3, out4, out5, out6;
wire stall_1;
assign stall_1 = 0;
Clock clock(clk);
testPC tpc(clk, stall, in1);
testA ta1(clk, stall, in1, out1);
testA ta2(clk, stall, out1, out2);
testA ta3(clk, stall, out2, out3);
testA ta4(clk, stall_1, out3, out4);
testA ta5(clk, stall_1, out4, out5);
testA ta6(clk, stall_1, out5, out6);
testB stl(clk, out1, stall);
initial begin
end
endmodule
module testA(clk, stall, in1, out1);
input clk, stall;
input[4:0] in1;
output reg[4:0] out1;
reg[4:0] temp1;
reg stallfinished;
initial begin
temp1 = 5'b00000;
out1 = 5'b00000;
stallfinished = 1'b0;
end
always @(posedge clk) begin
if(stall == 1'b1) out1 <= 5'b00000;
else if(stallfinished == 1'b1) begin
out1 <= temp1;
stallfinished <= 1'b0;
end
else out1 <= in1;
end
always @(posedge stall) begin
temp1 = in1;
end
always @(negedge stall) begin
stallfinished = 1'b1;
end
endmodule
module testB(clk, out1, stall);
input clk;
input[4:0] out1;
output reg stall;
integer i;
initial begin
stall = 1'b0;
i = 0;
end
always @(negedge clk)
if(i > 0) i = i-1;
else begin
if(out1 == 5'b00101) begin
i = 2;
stall = 1'b1;
end
else stall = 1'b0;
end
endmodule
module testPC(clk, stall, in1);
input clk, stall;
output reg[4:0] in1;
reg[4:0] PC;
initial begin
PC = 5'd0;
end
always @(posedge clk) begin
if(stall == 1'b0) PC <= PC+1;
in1 <= PC;
end
endmodule
/*
module test;
wire clk;
reg sig1;
reg[31:0] in1;
wire[31:0] out1, out2;
Clock clock(clk);
testA ta(clk, sig1, in1, out1, out2);
initial begin
sig1 <= 1'b0;
in1 <= 32'd0;
#100;
in1 <= 32'hffffffff;
#100;
sig1 <= 1'b1;
in1 <= 32'h0000ffff;
#100;
sig1 <= 1'b1;
in1 <= 32'hffff0000;
#100;
end
endmodule
module testA(clk, sig1, in1, out1, out2);
input clk, sig1;
input[31:0] in1;
output reg[31:0] out1, out2;
always @(posedge clk) begin
out1 <= in1;
if(sig1 == 1) out2 <= in1;
end
endmodule
*/
\ No newline at end of file
module testbench;
wire clk; // clock
reg[31:0] PC; // program counter
reg[31:0] instr_address;
wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
wire[31:0] instr; // loaded instruction.
wire[4:0] reg_writereg1; // register number for the write data.
wire[31:0] reg_writedata; // data that will be written in the register.
wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
wire[31:0] alu_input2; // input data of ALU.
wire[31:0] alu_result; // result data of ALU.
wire alu_branch; // indicator for branch operation.
wire[31:0] mem_readdata; // data from the requested address.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg;
wire[3:0] ctrl_aluctrl; // control signals.
wire[31:0] extend_output;
wire[31:0] shiftBranch_output;
wire[31:0] shiftJump_output;
Clock clock(clk);
InstructionMemory instrmem(instr_address, instr);
Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
Control ctrl(instr[31:26], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
Mux32bit mux_memtoreg(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC_branch);
Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
SignExtend extend(instr[15:0], extend_output);
Adder add_pc4(PC, 32'h00000004, addPC4);
Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
initial begin
PC = 32'h00000000;
end
always @(posedge clk) begin
case(nextPC[31]) // if nextPC is available, PC = nextPC.
1'b0: PC = nextPC;
1'b1: PC = nextPC;
endcase
instr_address = PC;
end
/*
wire clk; // clock
reg[31:0] PC, nextPC; // program counter
// Instruction Memory (IM)
reg[31:0] address; // instruction address. input of IM.
wire[31:0] instr; // loaded instruction. output of IM
// Register
reg[4:0] reg_readreg1, reg_readreg2; // register numbers of the read data. input of register.
reg[4:0] reg_writereg1; // register number for the write data. input of register.
reg[31:0] reg_writedata; // data that will be written in the register. input of register.
reg reg_sig_regwrite; // regwrite control signal. input of register
wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register. outputs of register.
// ALU
reg[31:0] alu_input1, alu_input2; // input data of ALU. inputs of ALU.
reg[3:0] alu_control; // ALU control signal. input of ALU.
wire[31:0] alu_result; // result data of ALU. output of ALU.
wire alu_branch; // indicator for branch operation. output of ALU.
//Data Memory (DM)
reg[31:0] mem_addr; // address of the read data. input of DM.
reg[31:0] mem_writedata; // data that will be written in the memory. input of DM.
reg mem_memread, mem_memwrite; // control signals for DM. input of DM.
wire[31:0] mem_readdata; // data from the requested address. output of DM.
// Control Unit
reg[5:0] ctrl_opcode; // opcode of the instruction. input of control unit.
wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread; // ??
wire ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump; // ??? control signals outputs of control unit.
wire[1:0] ctrl_aluop; // ??
// ALU Control Unit
reg[5:0] aluctrl_funct; // function code of the R type instructions. input of ALU control unit.
reg[1:0] aluctrl_aluop; // aluop signal. input of ALU control unit.
wire[3:0] aluctrl_sig; // alu control signal. output of ALU control unit.
// Multiplexer (Mux)
// mux_writereg Mux for Write Register.
reg[4:0] mux_writereg_input1, mux_writereg_input2;
reg mux_writereg_signal;
wire[4:0] mux_writereg_output;
// mux_alu Mux for ALU input 2.
reg[31:0] mux_alu_input1, mux_alu_input2;
reg mux_alu_signal;
wire[31:0] mux_alu_output;
// mux_writedata Mux for Write Data of Register.
reg[31:0] mux_writedata_input1, mux_writedata_input2;
reg mux_writedata_signal;
wire[31:0] mux_writedata_output;
// mux_branch Mux for Branch
reg[31:0] mux_branch_input1, mux_branch_input2;
reg mux_branch_signal;
wire[31:0] mux_branch_output;
// mux_jump Mux for Jump
reg[31:0] mux_jump_input1, mux_jump_input2;
reg mux_jump_signal;
wire[31:0] mux_jump_output;
// Sign Extend
reg[15:0] extend_input;
wire[31:0] extend_output;
// Adder
// add_pc4
reg[31:0] add_pc4_input; // input2 is 4.
wire[31:0] add_pc4_output;
// add_branch
reg[31:0] add_branch_input1, add_branch_input2;
wire[31:0] add_branch_output;
// Shift Left 2
// shiftBranch ShiftLeft2 which is used for Branch instructions.
reg[31:0] shiftBranch_input;
wire[31:0] shiftBranch_output;
// shiftJump ShiftLeft2 which is used for Jump instructions.
reg[31:0] shiftJump_input;
wire[31:0] shiftJump_output;
Clock clock(clk);
InstructionMemory instrmem(address, instr);
Register register(reg_readreg1, reg_readreg2, reg_writereg1, reg_writedata, reg_sig_regwrite, reg_readdata1, reg_readdata2);
ALU alu(alu_input1, alu_input2, alu_control, alu_result, alu_branch);
DataMemory datamem(mem_addr, mem_writedata, mem_memread, mem_memwrite, mem_readdata);
Control ctrl(ctrl_opcode, ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluop, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump);
ALUControl aluctrl(aluctrl_funct, aluctrl_aluop, aluctrl_sig);
Mux5bit mux_writereg(mux_writereg_input1, mux_writereg_input2, mux_writereg_signal, mux_writereg_output);
Mux32bit mux_alu(mux_alu_input1, mux_alu_input2, mux_alu_signal, mux_alu_output);
Mux32bit mux_writedata(mux_writedata_input1, mux_writedata_input2, mux_writedata_signal, mux_writedata_output);
Mux32bit mux_branch(mux_branch_input1, mux_branch_input2, mux_branch_signal, mux_branch_output);
Mux32bit mux_jump(mux_jump_input1, mux_jump_input2, mux_jump_signal, mux_jump_output);
SignExtend extend(extend_input, extend_output);
Adder add_pc4(add_pc4_input, 32'h00000004, add_pc4_output);
Adder add_branch(add_branch_input1, add_branch_input2, add_branch_output);
ShiftLeft2 shiftBranch(shiftBranch_input, shiftBranch_output);
ShiftLeft2 shiftJump(shiftJump_input, shiftJump_output);
initial begin
PC = 32'h00000000;
nextPC = 32'h00000000;
end
always @(posedge clk) begin
// IF
case(nextPC[0])
1'b0: PC = nextPC;
1'b1: PC = nextPC;
endcase
#1;
address = PC;
add_pc4_input = PC;
#1;
// ID
ctrl_opcode <= instr[31:26];
reg_readreg1 <= instr[25:21];
reg_readreg2 <= instr[20:16];
mux_writereg_input1 <= instr[20:16];
mux_writereg_input2 <= instr[15:11];
extend_input <= instr[15:0];
aluctrl_funct <= instr[5:0];
shiftJump_input <= {6'b000000, instr[25:0]};
#1;
mux_writereg_signal <= ctrl_regdst;
aluctrl_aluop <= ctrl_aluop;
// EX
mux_alu_input1 <= reg_readdata2;
mux_alu_input2 <= extend_output;
mux_alu_signal <= ctrl_alusrc;
shiftBranch_input <= extend_output;
#1;
alu_input1 <= reg_readdata1;
alu_input2 <= mux_alu_output;
alu_control <= aluctrl_sig;
add_branch_input1 <= add_pc4_output;
add_branch_input2 <= shiftBranch_output;
#1;
mux_branch_input1 <= add_pc4_output;
mux_branch_input2 <= add_branch_output;
mux_branch_signal <= ctrl_branch & alu_branch;
#1;
// MEM
mux_jump_input1 <= mux_branch_output;
mux_jump_input2 <= {add_pc4_output[31:28], shiftJump_output[27:0]};
mux_jump_signal <= ctrl_jump;
mem_addr <= alu_result;
mem_writedata <= reg_readdata2;
mem_memread <= ctrl_memread;
mem_memwrite <= ctrl_memwrite;
#1;
// WB
mux_writedata_input1 <= alu_result;
mux_writedata_input2 <= mem_readdata;
mux_writedata_signal <= ctrl_memtoreg;
#1;
reg_sig_regwrite <= ctrl_regwrite;
reg_writereg1 <= mux_writereg_output;
reg_writedata <= mux_writedata_output;
#1;
nextPC <= mux_jump_output;
end
*/
endmodule
# Reading C:/Modeltech_pe_edu_10.4a/tcl/vsim/pref.tcl
# OpenFile D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
No preview for this file type
......@@ -9,7 +9,7 @@ z2
cModel Technology
dC:/Modeltech_pe_edu_10.4a/examples
vAdder
Z0 !s110 1592320284
Z0 !s110 1592748174
!i10b 1
!s100 LKl?GBS:oo[A[hLP0Qb^_1
IlbJEP?2C3Ya>zhzD12^S]1
......@@ -23,7 +23,7 @@ Z4 OP;L;10.4a;61
r1
!s85 0
31
Z5 !s108 1592320284.000000
Z5 !s108 1592748173.000000
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
!s101 -O0
......@@ -45,7 +45,7 @@ R4
r1
!s85 0
31
R5
Z7 !s108 1592748174.000000
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
!s101 -O0
......@@ -53,7 +53,7 @@ R5
R6
n@a@l@u
vClock
Z7 !s110 1592320593
R0
!i10b 1
!s100 i65lY=7B8[4>bmAoJ2kDB2
IA2Ge3:5`hDcK4mi0FDSL[3
......@@ -67,15 +67,15 @@ R4
r1
!s85 0
31
Z11 !s108 1592320593.000000
Z12 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
Z13 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
R7
Z11 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
Z12 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
!s101 -O0
!i113 1
R6
n@clock
vClock_pipeline
R7
R0
!i10b 1
!s100 =@aPTZQSFah27j5MeG_d62
I8]3=4M<>=TGn3hX;LeQ183
......@@ -89,15 +89,15 @@ R4
r1
!s85 0
31
R7
R11
R12
R13
!s101 -O0
!i113 1
R6
n@clock_pipeline
vControl
Z14 !s110 1592320285
R0
!i10b 1
!s100 PKg@cjO2lUjfUI`iaE9QB2
IX2Ii?h^g2a@DaCi9:L8BU1
......@@ -111,7 +111,7 @@ R4
r1
!s85 0
31
Z15 !s108 1592320285.000000
R7
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v|
!s101 -O0
......@@ -119,7 +119,7 @@ Z15 !s108 1592320285.000000
R6
n@control
vDataMemory
R14
R0
!i10b 1
!s100 e=5E[GS05J<RCdT=KSMX_1
I9=L>R4ccfGY8^T;U50LY?1
......@@ -133,7 +133,7 @@ R4
r1
!s85 0
31
R15
R7
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v|
!s101 -O0
......@@ -141,123 +141,123 @@ R15
R6
n@data@memory
vEX_MEM
Z16 !s110 1592320286
Z13 !s110 1592748176
!i10b 1
!s100 k5Dc_]iZ1_]4AXAj8[5Y<1
IeKKdJcFcgGh?YcYVb3j^N0
R1
R2
Z17 w1592318419
Z18 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
Z19 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
Z14 w1592318419
Z15 8D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
Z16 FD:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
L0 123
R4
r1
!s85 0
31
Z20 !s108 1592320286.000000
Z21 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
Z22 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
Z17 !s108 1592748176.000000
Z18 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
Z19 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v|
!s101 -O0
!i113 1
R6
n@e@x_@m@e@m
vHazardHandling
R14
Z20 !s110 1592748175
!i10b 1
!s100 c>lJVMk@fzVaBjU0aV@h51
I:QLSJeiP@1NnaB^lRd6_l2
R1
R2
Z23 w1592320280
Z24 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
Z25 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
Z21 w1592320280
Z22 8D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
Z23 FD:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
L0 2
R4
r1
!s85 0
31
R15
Z26 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
Z27 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
Z24 !s108 1592748175.000000
Z25 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
Z26 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v|
!s101 -O0
!i113 1
R6
n@hazard@handling
vHazardHandling_Forwarding
R14
R20
!i10b 1
!s100 7f=OHLAZQeViCagN[c9Sf3
IZ44zQQI;2gGiN8L`RbQ<=1
R1
R2
R21
R22
R23
R24
R25
L0 93
R4
r1
!s85 0
31
R15
R24
R25
R26
R27
!s101 -O0
!i113 1
R6
n@hazard@handling_@forwarding
vID_EX
R16
R13
!i10b 1
!s100 H079WzWkDgiK]WV0i2=FW0
IH?JUEX4_FSm8PUM]MkZd41
R1
R2
R17
R18
R19
R14
R15
R16
L0 56
R4
r1
!s85 0
31
R20
R21
R22
R17
R18
R19
!s101 -O0
!i113 1
R6
n@i@d_@e@x
vIF_ID
R16
R13
!i10b 1
!s100 bKKM:?Mi3;B]TOe]O7<e>3
I[FaS1INGbXUlELb9411?G2
R1
R2
R17
R18
R19
R14
R15
R16
L0 27
R4
r1
!s85 0
31
R20
R21
R22
R17
R18
R19
!s101 -O0
!i113 1
R6
n@i@f_@i@d
vInstructionMemory
!s110 1592357290
R20
!i10b 1
!s100 5C;cU;MQ6jR<THFX]C[C_0
IYmf<mb=ca6ZWglS@o9l@c0
!s100 E683aVzbm`;9giCYOIXB@0
IcLd?ja5SSA2zhHQ<c02@N3
R1
R2
w1592357286
w1592746714
8D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
FD:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
L0 1
......@@ -265,7 +265,7 @@ R4
r1
!s85 0
31
!s108 1592357290.000000
R24
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v|
!s101 -O0
......@@ -273,29 +273,29 @@ r1
R6
n@instruction@memory
vMEM_WB
R16
R13
!i10b 1
!s100 FbXVboThZG;k@R0iW>;8`1
ITAUac1`E05Wn30@dIl3i`0
R1
R2
R17
R18
R19
R14
R15
R16
L0 172
R4
r1
!s85 0
31
R20
R21
R22
R17
R18
R19
!s101 -O0
!i113 1
R6
n@m@e@m_@w@b
vMIPS_Pipeline
R16
R20
!i10b 1
!s100 =YiG<BP8;FThR9<Of:]<42
Iz:PlBdl:5iijJ8LoFBAOe1
......@@ -309,7 +309,7 @@ R4
r1
!s85 0
31
R15
R24
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v|
!s101 -O0
......@@ -317,7 +317,7 @@ R15
R6
n@m@i@p@s_@pipeline
vMIPS_Pipeline_Forwarding
R16
R20
!i10b 1
!s100 0[k6421_Q:5fJX9:k0cCE0
I3WHKNdD6XohmDV_eiT8^c1
......@@ -331,7 +331,7 @@ R4
r1
!s85 0
31
R20
R24
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline_Forwarding.v|
!s101 -O0
......@@ -339,7 +339,7 @@ R20
R6
n@m@i@p@s_@pipeline_@forwarding
vMIPS_SingleCycle
R16
R13
!i10b 1
!s100 gM[;Cl]DhJhX67JceN9VX0
IEZ2gnb65W:EYTLgmRHR8f2
......@@ -353,7 +353,7 @@ R4
r1
!s85 0
31
R20
R24
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v|
!s101 -O0
......@@ -361,123 +361,123 @@ R20
R6
n@m@i@p@s_@single@cycle
vMux32bit
R16
R13
!i10b 1
!s100 foJG^YU75_eND1Og;6Z>O1
II3=gjhQD0_cn8mlDL]@bi1
R1
R2
R17
Z28 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
Z29 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
R14
Z27 8D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
Z28 FD:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
L0 15
R4
r1
!s85 0
31
R20
Z30 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
Z31 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
R17
Z29 !s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
Z30 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v|
!s101 -O0
!i113 1
R6
n@mux32bit
vMux5bit
R16
R13
!i10b 1
!s100 oSd=[kHDJb<:G7LN4]6@e3
IfiVXg_aB2GQG7?F@=HcEi0
R1
R2
R17
R14
R27
R28
R29
L0 1
R4
r1
!s85 0
31
R20
R17
R29
R30
R31
!s101 -O0
!i113 1
R6
n@mux5bit
vMux_Forwarding
R14
R20
!i10b 1
!s100 iCag5di1L;N5IB81hdLH>2
I:XNmLIF]Ed49A_PQCSjO=0
R1
R2
R21
R22
R23
R24
R25
L0 159
R4
r1
!s85 0
31
R15
R24
R25
R26
R27
!s101 -O0
!i113 1
R6
n@mux_@forwarding
vMuxBranchSignal
R16
R13
!i10b 1
!s100 H1RKS9h`Y6QFX88CRc<g[0
IGJT?gXMKEEWH?G^lPN79V2
R1
R2
R17
R14
R27
R28
R29
L0 29
R4
r1
!s85 0
31
R20
R17
R29
R30
R31
!s101 -O0
!i113 1
R6
n@mux@branch@signal
vPCregister
R16
R13
!i10b 1
!s100 ZWKU[XiaKQUFo0lg:i>8J3
IJN5hl<_id]kA5B6k4:9oE1
R1
R2
R17
R18
R19
R14
R15
R16
L0 1
R4
r1
!s85 0
31
R20
R21
R22
R17
R18
R19
!s101 -O0
!i113 1
R6
n@p@cregister
vRegister
Z32 !s110 1592320287
R13
!i10b 1
!s100 bC`<7GaPg=bDaZoUR<ADa0
I<aR5RJ2c1Qba>GdC]KZCd2
R1
R2
R17
R14
8D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
FD:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
L0 1
......@@ -485,7 +485,7 @@ R4
r1
!s85 0
31
Z33 !s108 1592320287.000000
R17
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v|
!s101 -O0
......@@ -493,13 +493,13 @@ Z33 !s108 1592320287.000000
R6
n@register
vShiftLeft2
R32
R13
!i10b 1
!s100 ]Zje9D[f?jFRnJBn`OeHc1
I]0TYJ]_7?FkOoY=2GlT5=3
R1
R2
R17
R14
8D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
FD:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
L0 1
......@@ -507,7 +507,7 @@ R4
r1
!s85 0
31
R33
R17
!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v|
!s101 -O0
......@@ -515,13 +515,13 @@ R33
R6
n@shift@left2
vSignExtend
R0
!s110 1592748173
!i10b 1
!s100 =4eXcc0im3]S=Kk@o:eh32
IFBiMm>fY8WE23A[Ye;CUj3
R1
R2
R17
R14
8D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
FD:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
L0 1
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