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Single Cycle branch 명령어 몇개 추가 및 pipeline register 추가

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Showing 31 changed files with 1204 additions and 627 deletions
...@@ -4,14 +4,15 @@ input clk; ...@@ -4,14 +4,15 @@ input clk;
4 input[31:0] aluin1, aluin2; 4 input[31:0] aluin1, aluin2;
5 input[3:0] aluctrl; 5 input[3:0] aluctrl;
6 output reg[31:0] aluout; 6 output reg[31:0] aluout;
7 -output alubranch; 7 +// output alubranch;
8 +output reg[5:0] alubranch;
8 9
9 reg overflow; 10 reg overflow;
10 reg[63:0] temp; 11 reg[63:0] temp;
11 reg[31:0] HI, LO; // HI, LO register for multiplication and division. 12 reg[31:0] HI, LO; // HI, LO register for multiplication and division.
12 reg[31:0] tempHI, tempLO; // temporary HI, LO register for multiplication and division. 13 reg[31:0] tempHI, tempLO; // temporary HI, LO register for multiplication and division.
13 14
14 -assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0; 15 +// assign alubranch = aluout == 32'h00000000 ? 1'b1 : 1'b0;
15 16
16 initial begin 17 initial begin
17 temp = 64'h0000000000000000; 18 temp = 64'h0000000000000000;
...@@ -33,6 +34,12 @@ case(aluctrl) ...@@ -33,6 +34,12 @@ case(aluctrl)
33 4'b0110: begin // sub 34 4'b0110: begin // sub
34 aluout = aluin1 - aluin2; 35 aluout = aluin1 - aluin2;
35 overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection. 36 overflow = aluin1[31]!=aluin2[31] && aluin1[31]!=aluout[31] ? 1'b1 : 1'b0; // overflow detection.
37 + alubranch[0] = (aluout == 32'd0) ? 1'b1 : 1'b0; // beq
38 + alubranch[1] = (aluout != 32'd0) ? 1'b1 : 1'b0; // bne
39 + alubranch[2] = (aluin1 > 32'd0) ? 1'b1 : 1'b0; // bgtz
40 + alubranch[3] = (aluin1 < 32'd0) ? 1'b1 : 1'b0; // bltz
41 + alubranch[4] = (aluin1 >= 32'd0) ? 1'b1 : 1'b0; // bgez
42 + alubranch[5] = (aluin1 <= 32'd0) ? 1'b1 : 1'b0; // blez
36 end 43 end
37 44
38 4'b0111: begin // slt 45 4'b0111: begin // slt
......
1 -module Control(opcode, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg); 1 +module Control(opcode, rt, funct, regdst, regwrite, alusrc, aluctrl, memread, memwrite, memtoreg, branch, jump, jumpreg);
2 2
3 input[5:0] opcode; 3 input[5:0] opcode;
4 +input[4:0] rt;
4 input[5:0] funct; 5 input[5:0] funct;
5 -output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, branch, jump, jumpreg; 6 +output reg regdst, regwrite, alusrc, memread, memwrite, memtoreg, jump, jumpreg;
6 output reg[3:0] aluctrl; 7 output reg[3:0] aluctrl;
8 +output reg[2:0] branch;
7 9
8 always @(*) begin 10 always @(*) begin
9 case(opcode) 11 case(opcode)
...@@ -14,7 +16,7 @@ always @(*) begin ...@@ -14,7 +16,7 @@ always @(*) begin
14 memread = 1'b0; 16 memread = 1'b0;
15 memwrite = 1'b0; 17 memwrite = 1'b0;
16 memtoreg = 1'b0; 18 memtoreg = 1'b0;
17 - branch = 1'b0; 19 + branch = 3'b000;
18 jump = 1'b0; 20 jump = 1'b0;
19 jumpreg = 1'b0; 21 jumpreg = 1'b0;
20 case(funct) 22 case(funct)
...@@ -41,7 +43,7 @@ always @(*) begin ...@@ -41,7 +43,7 @@ always @(*) begin
41 memread = 1'b0; 43 memread = 1'b0;
42 memwrite = 1'b0; 44 memwrite = 1'b0;
43 // memtoreg = 1'bx; 45 // memtoreg = 1'bx;
44 - branch = 1'b0; 46 + branch = 3'b000;
45 jump = 1'b1; 47 jump = 1'b1;
46 jumpreg = 1'b1; 48 jumpreg = 1'b1;
47 end 49 end
...@@ -57,7 +59,7 @@ always @(*) begin ...@@ -57,7 +59,7 @@ always @(*) begin
57 memread = 1'b0; 59 memread = 1'b0;
58 memwrite = 1'b0; 60 memwrite = 1'b0;
59 memtoreg = 1'b0; 61 memtoreg = 1'b0;
60 - branch = 1'b0; 62 + branch = 3'b000;
61 jump = 1'b0; 63 jump = 1'b0;
62 jumpreg = 1'b0; 64 jumpreg = 1'b0;
63 end 65 end
...@@ -70,7 +72,7 @@ always @(*) begin ...@@ -70,7 +72,7 @@ always @(*) begin
70 memread = 1'b0; 72 memread = 1'b0;
71 memwrite = 1'b0; 73 memwrite = 1'b0;
72 memtoreg = 1'b0; 74 memtoreg = 1'b0;
73 - branch = 1'b0; 75 + branch = 3'b000;
74 jump = 1'b0; 76 jump = 1'b0;
75 jumpreg = 1'b0; 77 jumpreg = 1'b0;
76 end 78 end
...@@ -83,20 +85,88 @@ always @(*) begin ...@@ -83,20 +85,88 @@ always @(*) begin
83 memread = 1'b0; 85 memread = 1'b0;
84 memwrite = 1'b0; 86 memwrite = 1'b0;
85 memtoreg = 1'b0; 87 memtoreg = 1'b0;
86 - branch = 1'b0; 88 + branch = 3'b000;
87 jump = 1'b0; 89 jump = 1'b0;
88 jumpreg = 1'b0; 90 jumpreg = 1'b0;
89 end 91 end
90 92
91 6'b000100: begin // beq instruction 93 6'b000100: begin // beq instruction
92 - // regdst = 1'bx; // don't care 94 + // regdst = 1'bx;
95 + regwrite = 1'b0;
96 + alusrc = 1'b0;
97 + aluctrl = 4'b0110; // sub
98 + memread = 1'b0;
99 + memwrite = 1'b0;
100 + // memtoreg = 1'bx;
101 + branch = 3'b001;
102 + jump = 1'b0;
103 + jumpreg = 1'b0;
104 + end
105 +
106 + 6'b000101: begin // bne instruction
107 + // regdst = 1'bx;
108 + regwrite = 1'b0;
109 + alusrc = 1'b0;
110 + aluctrl = 4'b0110; // sub
111 + memread = 1'b0;
112 + memwrite = 1'b0;
113 + // memtoreg = 1'bx;
114 + branch = 3'b010;
115 + jump = 1'b0;
116 + jumpreg = 1'b0;
117 + end
118 +
119 + 6'b000111: begin // bgtz instruction
120 + // regdst = 1'bx;
121 + regwrite = 1'b0;
122 + alusrc = 1'b0;
123 + aluctrl = 4'b0110; // sub
124 + memread = 1'b0;
125 + memwrite = 1'b0;
126 + // memtoreg = 1'bx;
127 + branch = 3'b011;
128 + jump = 1'b0;
129 + jumpreg = 1'b0;
130 + end
131 +
132 + 6'b000001: begin
133 + case(rt)
134 + 5'b00000: begin // bltz instruction
135 + // regdst = 1'bx;
136 + regwrite = 1'b0;
137 + alusrc = 1'b0;
138 + aluctrl = 4'b0110; // sub
139 + memread = 1'b0;
140 + memwrite = 1'b0;
141 + // memtoreg = 1'bx;
142 + branch = 3'b100;
143 + jump = 1'b0;
144 + jumpreg = 1'b0;
145 + end
146 + 5'b00001: begin // bgez instruction
147 + // regdst = 1'bx;
148 + regwrite = 1'b0;
149 + alusrc = 1'b0;
150 + aluctrl = 4'b0110; // sub
151 + memread = 1'b0;
152 + memwrite = 1'b0;
153 + // memtoreg = 1'bx;
154 + branch = 3'b101;
155 + jump = 1'b0;
156 + jumpreg = 1'b0;
157 + end
158 + endcase
159 + end
160 +
161 + 6'b000111: begin // blez instruction
162 + // regdst = 1'bx;
93 regwrite = 1'b0; 163 regwrite = 1'b0;
94 alusrc = 1'b0; 164 alusrc = 1'b0;
95 aluctrl = 4'b0110; // sub 165 aluctrl = 4'b0110; // sub
96 memread = 1'b0; 166 memread = 1'b0;
97 memwrite = 1'b0; 167 memwrite = 1'b0;
98 // memtoreg = 1'bx; 168 // memtoreg = 1'bx;
99 - branch = 1'b1; 169 + branch = 3'b110;
100 jump = 1'b0; 170 jump = 1'b0;
101 jumpreg = 1'b0; 171 jumpreg = 1'b0;
102 end 172 end
...@@ -109,7 +179,7 @@ always @(*) begin ...@@ -109,7 +179,7 @@ always @(*) begin
109 memread = 1'b0; 179 memread = 1'b0;
110 memwrite = 1'b0; 180 memwrite = 1'b0;
111 // memtoreg = 1'bx; 181 // memtoreg = 1'bx;
112 - branch = 1'b0; 182 + branch = 3'b000;
113 jump = 1'b1; 183 jump = 1'b1;
114 jumpreg = 1'b0; 184 jumpreg = 1'b0;
115 end 185 end
...@@ -122,7 +192,7 @@ always @(*) begin ...@@ -122,7 +192,7 @@ always @(*) begin
122 memread = 1'b1; 192 memread = 1'b1;
123 memwrite = 1'b0; 193 memwrite = 1'b0;
124 memtoreg = 1'b1; 194 memtoreg = 1'b1;
125 - branch = 1'b0; 195 + branch = 3'b000;
126 jump = 1'b0; 196 jump = 1'b0;
127 jumpreg = 1'b0; 197 jumpreg = 1'b0;
128 end 198 end
...@@ -135,7 +205,7 @@ always @(*) begin ...@@ -135,7 +205,7 @@ always @(*) begin
135 memread = 1'b0; 205 memread = 1'b0;
136 memwrite = 1'b1; 206 memwrite = 1'b1;
137 // memtoreg = 1'bx; 207 // memtoreg = 1'bx;
138 - branch = 1'b0; 208 + branch = 3'b000;
139 jump = 1'b0; 209 jump = 1'b0;
140 jumpreg = 1'b0; 210 jumpreg = 1'b0;
141 end 211 end
...@@ -148,7 +218,7 @@ always @(*) begin ...@@ -148,7 +218,7 @@ always @(*) begin
148 memread = 1'b0; 218 memread = 1'b0;
149 memwrite = 1'b0; 219 memwrite = 1'b0;
150 // memtoreg = 1'bx; 220 // memtoreg = 1'bx;
151 - branch = 1'b0; 221 + branch = 3'b000;
152 jump = 1'b0; 222 jump = 1'b0;
153 jumpreg = 1'b0; 223 jumpreg = 1'b0;
154 end 224 end
......
1 +/* Not Finished */
2 +module Stall(clk, in_readreg_num1, in_readreg_num2, in_writereg_num);
3 +
4 +input clk;
5 +input[4:0] in_readreg_num1, in_readreg_num2, in_writereg_num;
6 +
7 +reg[4:0] writeregs;
8 +
9 +endmodule
10 +
11 +
1 +module InstructionMemory(address, instruction);
2 +
3 +input[31:0] address;
4 +output reg[31:0] instruction;
5 +
6 +reg[31:0] instr_mem[127:0];
7 +
8 +initial begin
9 +instr_mem[0] = 32'd0;
10 +instr_mem[1] = 32'b00100100000010000000000011111111; // addi, $0 $8 255
11 +instr_mem[2] = 32'b00000001000010000100100000100000; // add, $8 $8 $9
12 +instr_mem[3] = 32'b00000001000000000101000000100000; // add, $8 $0 $10
13 +instr_mem[4] = 32'b00010001000010100000000000000001; // beq, $8 $10 +1
14 +instr_mem[5] = 32'd0;
15 +instr_mem[6] = 32'b00000001000010010000000000011000; // mult, $8 $9
16 +instr_mem[7] = 32'd0;
17 +instr_mem[8] = 32'b00000000000000000110000000010000; // mfhi, $12
18 +instr_mem[9] = 32'b00000000000000000110100000010010; // mflo, $13
19 +instr_mem[10] = 32'b10101100000011010000000000111100; // sw, $0 $13 60
20 +instr_mem[11] = 32'd0;
21 +instr_mem[12] = 32'b00010001000010110000000000000001; // beq, $8 $11 +1
22 +instr_mem[13] = 32'b10001100000000010000000000111100; // lw, $0 $1 60
23 +instr_mem[14] = 32'd0;
24 +instr_mem[15] = 32'b00000000000000000000000000001000; // jr, $0
25 +
26 +end
27 +
28 +always @ (*) begin
29 + instruction = instr_mem[address/4];
30 +end
31 +
32 +endmodule
1 +D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/testbench.v
2 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 +-- Compiling module testbench
4 +
5 +Top level modules:
6 + testbench
7 +
8 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/test.v
9 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 +-- Compiling module test
11 +-- Compiling module testA
12 +
13 +Top level modules:
14 + test
15 +
16 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
17 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
18 +-- Compiling module Adder
19 +
20 +Top level modules:
21 + Adder
22 +
23 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_SingleCycle.v
24 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
25 +-- Compiling module MIPS_SingleCycle
26 +
27 +Top level modules:
28 + MIPS_SingleCycle
29 +
30 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/InstructionMemory.v
31 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
32 +-- Compiling module InstructionMemory
33 +
34 +Top level modules:
35 + InstructionMemory
36 +
37 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Register.v
38 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
39 +-- Compiling module Register
40 +
41 +Top level modules:
42 + Register
43 +
44 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/PipelineRegisters.v
45 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
46 +-- Compiling module IF_ID
47 +-- Compiling module ID_EX
48 +-- Compiling module EX_MEM
49 +-- Compiling module MEM_WB
50 +-- Compiling module PCcounter
51 +
52 +Top level modules:
53 + IF_ID
54 + ID_EX
55 + EX_MEM
56 + MEM_WB
57 + PCcounter
58 +
59 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/MIPS_Pipeline.v
60 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
61 +-- Compiling module MIPS_Pipeline
62 +
63 +Top level modules:
64 + MIPS_Pipeline
65 +
66 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/HazardHandling.v
67 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
68 +-- Compiling module Stall
69 +
70 +Top level modules:
71 + Stall
72 +
73 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/SignExtend.v
74 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
75 +-- Compiling module SignExtend
76 +
77 +Top level modules:
78 + SignExtend
79 +
80 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Control.v
81 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
82 +-- Compiling module Control
83 +
84 +Top level modules:
85 + Control
86 +
87 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/Mux.v
88 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
89 +-- Compiling module Mux5bit
90 +-- Compiling module Mux32bit
91 +-- Compiling module MuxBranchSignal
92 +
93 +Top level modules:
94 + Mux5bit
95 + Mux32bit
96 + MuxBranchSignal
97 +
98 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
99 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
100 +-- Compiling module ALU
101 +
102 +Top level modules:
103 + ALU
104 +
105 +} {} {}} {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/MIPS/Data Memory.v}
106 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
107 +-- Compiling module DataMemory
108 +
109 +Top level modules:
110 + DataMemory
111 +
112 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/ShiftLeft2.v
113 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
114 +-- Compiling module ShiftLeft2
115 +
116 +Top level modules:
117 + ShiftLeft2
118 +
119 +} {} {}} D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
120 +Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
121 +-- Compiling module Clock
122 +
123 +Top level modules:
124 + Clock
125 +
126 +} {} {}}
1 +// Test Required
2 +module MIPS_Pipeline;
3 +
4 +wire clk; // clock
5 +wire[31:0] instr_address, addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
6 +
7 +wire[31:0] instr; // loaded instruction.
8 +
9 +wire[4:0] reg_writereg1; // register number for the write data.
10 +wire[31:0] reg_writedata; // data that will be written in the register.
11 +wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
12 +
13 +wire[31:0] alu_input2; // input data of ALU.
14 +wire[31:0] alu_result; // result data of ALU.
15 +wire[5:0] alu_branch; // indicator for branch operation.
16 +
17 +wire[31:0] mem_readdata; // data from the requested address.
18 +
19 +wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
20 +wire[3:0] ctrl_aluctrl; // control signals.
21 +wire[2:0] ctrl_branch;
22 +
23 +wire[31:0] extend_output;
24 +
25 +wire[31:0] shiftBranch_output;
26 +wire[31:0] shiftJump_output;
27 +
28 +// IF_ID register outputs
29 +wire[31:0] ifid_instr, ifid_PC_4;
30 +
31 +// ID_EX register outputs
32 +wire[4:0] idex_writereg1, idex_readreg_num1, idex_readreg_num2;
33 +wire idex_regwrite, idex_alusrc, idex_memread, idex_memwrite, idex_memtoreg, idex_jump, idex_jumpreg;
34 +wire[3:0] idex_aluctrl;
35 +wire[2:0] idex_branch;
36 +wire[31:0] idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump;
37 +
38 +// EX_MEM register outputs
39 +wire[4:0] exmem_writereg1;
40 +wire exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump;
41 +wire[31:0] exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch;
42 +
43 +// MEM_WB register outputs
44 +wire[4:0] memwb_writereg1;
45 +wire memwb_regwrite, memwb_memtoreg, memwb_jump;
46 +wire[31:0] memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump;
47 +
48 +
49 +Clock clock(clk);
50 +PCcounter pccounter(clk, nextPC, instr_address);
51 +
52 +// Instruction Fetch
53 +InstructionMemory instrmem(instr_address, instr);
54 +Adder add_pc4(PC, 32'h00000004, addPC4);
55 +
56 +IF_ID ifid(clk, instr, addPC4,
57 + ifid_instr, ifid_PC_4);
58 +
59 +// Instruction Decode
60 +Control ctrl(ifid_instr[31:26], ifid_instr[20:16], ifid_instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
61 +Mux5bit mux_regdst(ifid_instr[20:16], ifid_instr[15:11], ctrl_regdst, reg_writereg1);
62 +Register register(clk, ifid_instr[25:21], ifid_instr[20:16], memwb_writereg1, reg_writedata, memwb_regwrite, reg_readdata1, reg_readdata2);
63 +SignExtend extend(ifid_instr[15:0], extend_output);
64 +ShiftLeft2 shiftJump({6'b000000, ifid_instr[25:0]}, shiftJump_output);
65 +
66 +ID_EX idex(clk, reg_writereg1, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg,
67 + reg_readdata1, reg_readdata2, extend_output, ifid_PC_4, shiftJump_output, ifid_instr[25:21], ifid_instr[20:16],
68 + idex_writereg1, idex_regwrite, idex_alusrc, idex_aluctrl, idex_memread, idex_memwrite, idex_memtoreg, idex_branch, idex_jump, idex_jumpreg,
69 + idex_readdata1, idex_readdata2, idex_extenddata, idex_PC_4, idex_tempPCjump, idex_readreg_num1, idex_readreg_num2);
70 +
71 +// Execute
72 +Mux32bit mux_alusrc(idex_readdata2, idex_extend, idex_alusrc, alu_input2);
73 +ALU alu(clk, idex_readdata1, alu_input2, idex_aluctrl, alu_result, alu_branch);
74 +ShiftLeft2 shiftBranch(idex_extend, shiftBranch_output);
75 +Adder add_branch(idex_addPC4, shiftBranch_output, addPCbranch);
76 +MuxBranchSignal mux_branchsignal(alu_branch, idex_branch, branch_signal);
77 +Mux32bit mux_jumpreg({idex_PC_4[31:28], idex_tempPCjump[27:0]}, idex_readdata1, idex_jumpreg, tempPC_jump);
78 +
79 +EX_MEM ex_mem(clk, idex_writereg1, idex_regwrite, idex_memread, idex_memwrite, idex_memtoreg, branch_signal, idex_jump,
80 + alu_result, idex_readdata2, idex_PC_4, tempPC_jump, addPCbranch,
81 + exmem_writereg1, exmem_regwrite, exmem_memread, exmem_memwrite, exmem_memtoreg, exmem_branch, exmem_jump,
82 + exmem_aluresult, exmem_memwritedata, exmem_PC_4, exmem_PCjump, exmem_tempPCbranch);
83 +
84 +// Memory
85 +DataMemory datamem(clk, exmem_aluresult, exmem_memwritedata, exmem_memread, exmem_memwrite, mem_readdata);
86 +Mux32bit mux_branch(exmem_PC_4, exmem_tempPCbranch, exmem_branch , tempPC_branch);
87 +
88 +MEM_WB mem_wb(clk, exmem_writereg1, exmem_regwrite, exmem_memtoreg, exmem_jump,
89 + exmem_aluresult, mem_readdata, tempPC_branch, exmem_PCjump,
90 + memwb_writereg1, memwb_regwrite, memwb_memtoreg, memwb_jump,
91 + memwb_aluresult, memwb_memreaddata, memwb_PCbranch, memwb_PCjump);
92 +
93 +// Writeback
94 +Mux32bit mux_memtoreg(memwb_aluresult, memwb_memreaddata, memwb_memtoreg, reg_writedata);
95 +Mux32bit mux_jump(memwb_PCbranch, memwb_PCjump, memwb_jump, nextPC);
96 +
97 +
98 +
99 +
100 +always @(posedge clk) begin
101 +
102 +end
103 +
104 +/*
105 +wire clk; // clock
106 +reg[31:0] PC, instr_address;
107 +
108 +// IF - ID
109 +wire[31:0] if_id_instruction, if_id_pc_4;
110 +
111 +// ID - EX
112 +wire[31:0] id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump;
113 +wire[4:0] id_ex_writereg, id_hh_readreg1, id_hh_readreg2;
114 +wire id_ex_regwrite, id_ex_alusrc, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg;
115 +wire[3:0] id_ex_aluctrl;
116 +
117 +// EX - MEM
118 +wire[31:0] ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch;
119 +wire[4:0] ex_mem_writereg;
120 +wire ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump;
121 +
122 +// MEM - WB
123 +wire[4:0] mem_wb_writereg_num;
124 +wire mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump;
125 +wire[31:0] mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump;
126 +
127 +// WB - etc.
128 +wire wb_id_regwrite;
129 +wire[4:0] wb_id_writereg;
130 +wire[31:0] wb_id_reg_writedata;
131 +wire[31:0] wb_nextPC;
132 +
133 +Clock clock(clk);
134 +
135 +InstructionFetch IF(clk, PC, if_id_instruction, if_id_pc_4);
136 +
137 +InstructionDecode ID(clk, if_id_instruction, if_id_pc_4, wb_id_writereg, wb_id_reg_writedata, wb_id_regwrite,
138 + id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
139 + id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump);
140 +
141 +Execute EX(clk, id_ex_writereg, id_ex_regwrite, id_ex_alusrc, id_ex_aluctrl, id_ex_memread, id_ex_memwrite, id_ex_memtoreg, id_ex_branch, id_ex_jump, id_ex_jumpreg,
142 + id_ex_reg_readdata1, id_ex_reg_readdata2, id_ex_extenddata, id_ex_pc_4, id_ex_tempPCjump,
143 + ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump,
144 + ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch);
145 +
146 +Mem MEM(clk, ex_mem_writereg, ex_mem_regwrite, ex_mem_memread, ex_mem_memwrite, ex_mem_memtoreg, ex_mem_branch, ex_mem_jump,
147 + ex_mem_aluresult, ex_mem_memwritedata, ex_mem_PC_4, ex_mem_PCjump, ex_mem_tempPCbranch,
148 + mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump);
149 +
150 +WriteBack WB(clk, mem_wb_writereg_num, mem_wb_regwrite, mem_wb_memtoreg, mem_wb_jump, mem_wb_aluresult, mem_wb_memreaddata, mem_wb_PCbranch, mem_wb_PCjump,
151 + wb_id_regwrite, wb_id_writereg, wb_id_reg_writedata, wb_nextPC);
152 +
153 +initial begin
154 + PC = 32'hfffffffc;
155 +end
156 +
157 +always @(posedge clk) begin
158 + instr_address = PC;
159 +end
160 +
161 +always @(negedge clk) begin
162 + PC = PC + 4;
163 +end
164 +*/
165 +endmodule
1 +module MIPS_SingleCycle;
2 +
3 +wire clk; // clock
4 +reg[31:0] PC; // program counter
5 +reg[31:0] instr_address;
6 +wire[31:0] addPC4, addPCbranch, tempPC_branch, tempPC_jump, nextPC;
7 +
8 +wire[31:0] instr; // loaded instruction.
9 +
10 +wire[4:0] reg_writereg1; // register number for the write data.
11 +wire[31:0] reg_writedata; // data that will be written in the register.
12 +wire[31:0] reg_readdata1, reg_readdata2; // data from the requested register.
13 +
14 +wire[31:0] alu_input2; // input data of ALU.
15 +wire[31:0] alu_result; // result data of ALU.
16 +wire[5:0] alu_branch; // indicator for branch operation.
17 +
18 +wire[31:0] mem_readdata; // data from the requested address.
19 +
20 +wire ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_jump, ctrl_jumpreg, branch_signal;
21 +wire[3:0] ctrl_aluctrl;
22 +wire[2:0] ctrl_branch; // control signals.
23 +
24 +wire[31:0] extend_output;
25 +
26 +wire[31:0] shiftBranch_output;
27 +wire[31:0] shiftJump_output;
28 +
29 +Clock clock(clk);
30 +InstructionMemory instrmem(instr_address, instr);
31 +Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ctrl_regwrite, reg_readdata1, reg_readdata2);
32 +ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
33 +DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
34 +Control ctrl(instr[31:26], instr[20:16], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
35 +Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
36 +MuxBranchSignal mux_branchsignal(alu_branch, ctrl_branch, branch_signal);
37 +Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
38 +Mux32bit mux_memtoreg(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
39 +Mux32bit mux_branch(addPC4, addPCbranch, branch_signal , tempPC_branch);
40 +Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
41 +Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
42 +SignExtend extend(instr[15:0], extend_output);
43 +Adder add_pc4(PC, 32'h00000004, addPC4);
44 +Adder add_branch(addPC4, shiftBranch_output, addPCbranch);
45 +ShiftLeft2 shiftBranch(extend_output, shiftBranch_output);
46 +ShiftLeft2 shiftJump({6'b000000, instr[25:0]}, shiftJump_output);
47 +
48 +initial begin
49 + PC = 32'h00000000;
50 +end
51 +
52 +always @(posedge clk) begin
53 + case(nextPC[31]) // if nextPC is available, PC = nextPC.
54 + 1'b0: PC = nextPC;
55 + 1'b1: PC = nextPC;
56 + endcase
57 +
58 + instr_address = PC;
59 +end
60 +
61 +endmodule
1 module Mux5bit(input1, input2, signal, output1); 1 module Mux5bit(input1, input2, signal, output1);
2 -
3 input[4:0] input1, input2; 2 input[4:0] input1, input2;
4 input signal; 3 input signal;
5 output reg[4:0] output1; 4 output reg[4:0] output1;
...@@ -10,11 +9,10 @@ always @(*) begin ...@@ -10,11 +9,10 @@ always @(*) begin
10 1'b1: output1 = input2; 9 1'b1: output1 = input2;
11 endcase 10 endcase
12 end 11 end
13 -
14 endmodule 12 endmodule
15 13
16 -module Mux32bit(input1, input2, signal, output1);
17 14
15 +module Mux32bit(input1, input2, signal, output1);
18 input[31:0] input1, input2; 16 input[31:0] input1, input2;
19 input signal; 17 input signal;
20 output reg[31:0] output1; 18 output reg[31:0] output1;
...@@ -25,5 +23,24 @@ always @(*) begin ...@@ -25,5 +23,24 @@ always @(*) begin
25 1'b1: output1 = input2; 23 1'b1: output1 = input2;
26 endcase 24 endcase
27 end 25 end
26 +endmodule
27 +
28 +
29 +module MuxBranchSignal(input1, signal, output1);
30 +input[5:0] input1;
31 +input[2:0] signal;
32 +output reg output1;
33 +
34 +always @(*) begin
35 + case(signal)
36 + 3'b000: output1 = 1'b0;
37 + 3'b001: output1 = input1[0];
38 + 3'b010: output1 = input1[1];
39 + 3'b011: output1 = input1[2];
40 + 3'b100: output1 = input1[3];
41 + 3'b101: output1 = input1[4];
42 + 3'b110: output1 = input1[5];
43 + endcase
44 +end
28 45
29 endmodule 46 endmodule
......
1 +module IF_ID(clk, in_instruction, in_PC_4,
2 + out_instruction, out_PC_4);
3 +input clk;
4 +input[31:0] in_instruction, in_PC_4;
5 +output reg[31:0] out_instruction, out_PC_4;
6 +
7 +always @(posedge clk) begin
8 + out_instruction <= in_instruction;
9 + out_PC_4 <= in_PC_4;
10 +end
11 +endmodule
12 +
13 +
14 +module ID_EX(clk, in_writereg_num, in_regwrite, in_alusrc, in_aluctrl, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg,
15 + in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2,
16 + out_writereg_num, out_regwrite, out_alusrc, out_aluctrl, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg,
17 + out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2);
18 +input clk;
19 +input[4:0] in_writereg_num;
20 +input in_regwrite, in_alusrc, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump, in_jumpreg;
21 +input[3:0] in_aluctrl;
22 +input[31:0] in_readdata1, in_readdata2, in_extenddata, in_PC_4, in_tempPCjump, in_readreg_num1, in_readreg_num2;
23 +output reg[4:0] out_writereg_num;
24 +output reg out_regwrite, out_alusrc, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump, out_jumpreg;
25 +output reg[3:0] out_aluctrl;
26 +output reg[31:0] out_readdata1, out_readdata2, out_extenddata, out_PC_4, out_tempPCjump, out_readreg_num1, out_readreg_num2;
27 +
28 +always @(posedge clk) begin
29 + out_writereg_num <= in_writereg_num;
30 + out_regwrite <= in_regwrite;
31 + out_alusrc <= in_alusrc;
32 + out_aluctrl <= in_aluctrl;
33 + out_memread <= in_memread;
34 + out_memwrite <= in_memwrite;
35 + out_memtoreg <= in_memtoreg;
36 + out_branch <= in_branch;
37 + out_jump <= in_jump;
38 + out_jumpreg <= in_jumpreg;
39 +
40 + out_readdata1 <= in_readdata1;
41 + out_readdata2 <= in_readdata2;
42 + out_extenddata <= in_extenddata;
43 + out_PC_4 <= out_PC_4;
44 + out_tempPCjump <= in_tempPCjump;
45 + out_readreg_num1 <= in_readreg_num1;
46 + out_readreg_num2 <= in_readreg_num2;
47 +end
48 +endmodule
49 +
50 +
51 +module EX_MEM(clk, in_writereg_num, in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump,
52 + in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch,
53 + out_writereg_num, out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump,
54 + out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch);
55 +input clk;
56 +input[4:0] in_writereg_num;
57 +input in_regwrite, in_memread, in_memwrite, in_memtoreg, in_branch, in_jump;
58 +input[31:0] in_aluresult, in_mem_writedata, in_PC_4, in_PCjump, in_tempPCbranch;
59 +output reg[4:0] out_writereg_num;
60 +output reg out_regwrite, out_memread, out_memwrite, out_memtoreg, out_branch, out_jump;
61 +output reg[31:0] out_aluresult, out_mem_writedata, out_PC_4, out_PCjump, out_tempPCbranch;
62 +
63 +always @(posedge clk) begin
64 + out_writereg_num <= in_writereg_num;
65 + out_regwrite <= in_regwrite;
66 + out_memread <= in_memread;
67 + out_memwrite <= in_memwrite;
68 + out_memtoreg <= in_memtoreg;
69 + out_branch <= in_branch;
70 + out_jump <= in_jump;
71 +
72 + out_aluresult <= in_aluresult;
73 + out_mem_writedata <= in_mem_writedata;
74 + out_PC_4 <= in_PC_4;
75 + out_PCjump <= in_PCjump;
76 + out_tempPCbranch <= in_tempPCbranch;
77 +end
78 +endmodule
79 +
80 +
81 +module MEM_WB(clk, in_writereg_num, in_regwrite, in_memtoreg, in_jump, in_aluresult, in_memreaddata, in_PCbranch, in_PCjump,
82 + out_writereg_num, out_regwrite, out_memtoreg, out_jump, out_aluresult, out_memreaddata, out_PCbranch, out_PCjump);
83 +input clk;
84 +input[4:0] in_writereg_num;
85 +input in_regwrite, in_memtoreg, in_jump;
86 +input[31:0] in_aluresult, in_memreaddata, in_PCbranch, in_PCjump;
87 +output reg[4:0] out_writereg_num;
88 +output reg out_regwrite, out_memtoreg, out_jump;
89 +output reg[31:0] out_aluresult, out_memreaddata, out_PCbranch, out_PCjump;
90 +
91 +always @(posedge clk) begin
92 + out_writereg_num <= in_writereg_num;
93 + out_regwrite <= in_regwrite;
94 + out_memtoreg <= in_memtoreg;
95 + out_jump <= in_jump;
96 +
97 + out_aluresult <= in_aluresult;
98 + out_memreaddata <= in_memreaddata;
99 + out_PCbranch <= out_PCbranch;
100 + out_PCjump <= out_PCjump;
101 +end
102 +endmodule
103 +
104 +/* Not Finished */
105 +module PCcounter(clk, in_pc, out_nextpc);
106 +input clk;
107 +input[31:0] in_pc;
108 +output reg[31:0] out_nextpc;
109 +reg[31:0] PC;
110 +
111 +initial begin
112 + PC = 32'h00000000;
113 +end
114 +
115 +always @(posedge clk) begin
116 +/*
117 + case(in_pc[31]) // if in_pc is available, PC = in_pc.
118 + 1'b0: PC = in_pc;
119 + 1'b1: PC = in_pc;
120 + endcase
121 +*/
122 + PC <= PC+4;
123 + out_nextpc <= PC;
124 +end
125 +
126 +endmodule
1 +module test;
2 +
3 +wire clk;
4 +reg sig1;
5 +reg[31:0] in1;
6 +wire[31:0] out1, out2;
7 +
8 +Clock clock(clk);
9 +testA ta(clk, sig1, in1, out1, out2);
10 +
11 +initial begin
12 + sig1 <= 1'b0;
13 + in1 <= 32'd0;
14 + #100;
15 + in1 <= 32'hffffffff;
16 + #100;
17 + sig1 <= 1'b1;
18 + in1 <= 32'h0000ffff;
19 + #100;
20 + sig1 <= 1'b1;
21 + in1 <= 32'hffff0000;
22 + #100;
23 +end
24 +
25 +/*
26 +wire clk;
27 +reg[31:0] pc;
28 +wire[31:0] instr, tempPC;
29 +
30 +Clock clock(clk);
31 +InstructionFetch IF(clk, pc, instr, tempPC);
32 +
33 +initial begin
34 + pc = 32'hfffffffc;
35 +end
36 +
37 +always @(negedge clk) begin
38 + pc = pc + 4;
39 +end
40 +*/
41 +endmodule
42 +
43 +module testA(clk, sig1, in1, out1, out2);
44 +
45 +input clk, sig1;
46 +input[31:0] in1;
47 +output reg[31:0] out1, out2;
48 +
49 +always @(posedge clk) begin
50 + out1 <= in1;
51 + if(sig1 == 1) out2 <= in1;
52 +end
53 +
54 +endmodule
...@@ -31,9 +31,9 @@ Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata, ...@@ -31,9 +31,9 @@ Register register(clk, instr[25:21], instr[20:16], reg_writereg1, reg_writedata,
31 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch); 31 ALU alu(clk, reg_readdata1, alu_input2, ctrl_aluctrl, alu_result, alu_branch);
32 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata); 32 DataMemory datamem(clk, alu_result, reg_readdata2, ctrl_memread, ctrl_memwrite, mem_readdata);
33 Control ctrl(instr[31:26], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg); 33 Control ctrl(instr[31:26], instr[5:0], ctrl_regdst, ctrl_regwrite, ctrl_alusrc, ctrl_aluctrl, ctrl_memread, ctrl_memwrite, ctrl_memtoreg, ctrl_branch, ctrl_jump, ctrl_jumpreg);
34 -Mux5bit mux_writereg(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1); 34 +Mux5bit mux_regdst(instr[20:16], instr[15:11], ctrl_regdst, reg_writereg1);
35 -Mux32bit mux_alu(reg_readdata2, extend_output, ctrl_alusrc, alu_input2); 35 +Mux32bit mux_alusrc(reg_readdata2, extend_output, ctrl_alusrc, alu_input2);
36 -Mux32bit mux_writedata(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata); 36 +Mux32bit mux_memtoreg(alu_result, mem_readdata, ctrl_memtoreg, reg_writedata);
37 Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC_branch); 37 Mux32bit mux_branch(addPC4, addPCbranch, {ctrl_branch&alu_branch} , tempPC_branch);
38 Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump); 38 Mux32bit mux_jumpreg({addPC4[31:28], shiftJump_output[27:0]}, reg_readdata1, ctrl_jumpreg, tempPC_jump);
39 Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC); 39 Mux32bit mux_jump(tempPC_branch, tempPC_jump, ctrl_jump, nextPC);
......
1 +m255
2 +K4
3 +z2
4 +13
5 +!s112 1.1
6 +!i10d 8192
7 +!i10e 25
8 +!i10f 100
9 +cModel Technology
10 +dD:/class/Capstone1/KNW_Project2/Project/Pipeline
11 +vAdder
12 +!s110 1590758368
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17 +Z1 dD:/class/Capstone1/KNW_Project2/Project/MIPS
18 +Z2 w1590245372
19 +8D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
20 +FD:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v
21 +L0 1
22 +Z3 OP;L;10.4a;61
23 +r1
24 +!s85 0
25 +31
26 +!s108 1590758368.000000
27 +!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
28 +!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/Adder.v|
29 +!s101 -O0
30 +!i113 1
31 +Z4 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0
32 +n@adder
33 +vALU
34 +Z5 !s110 1590758369
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36 +!s100 8`_QAORX^JgbcU:FJndD:1
37 +I^ma26jUAmP4?NRZPY^4G=2
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39 +R1
40 +w1590755442
41 +8D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
42 +FD:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v
43 +L0 1
44 +R3
45 +r1
46 +!s85 0
47 +31
48 +Z6 !s108 1590758369.000000
49 +!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
50 +!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/ALU.v|
51 +!s101 -O0
52 +!i113 1
53 +R4
54 +n@a@l@u
55 +vClock
56 +R5
57 +!i10b 1
58 +!s100 OWQXV6kDYiT>ChTOoCFa]2
59 +IQHn8SmB<S>;8X8GE^RU_a0
60 +R0
61 +R1
62 +R2
63 +8D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
64 +FD:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v
65 +L0 1
66 +R3
67 +r1
68 +!s85 0
69 +31
70 +R6
71 +!s107 D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
72 +!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/MIPS/clock.v|
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1 -module InstructionMemory(address, instruction);
2 -
3 -input[31:0] address;
4 -output reg[31:0] instruction;
5 -
6 -reg[31:0] instr_mem[127:0];
7 -
8 -initial begin
9 -instr_mem[0] = 32'd0;
10 -instr_mem[1] = 32'b00100100000010000000000011111111; // addi $0 $8 255
11 -instr_mem[2] = 32'b00000001000010000100100000100000; // add $8 $8 $9
12 -instr_mem[3] = 32'b00000001000000000101000000100000; // add $8 $0 $10
13 -instr_mem[4] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
14 -instr_mem[5] = 32'b00000001000010010000000000011000; // mult $8 $9
15 -instr_mem[6] = 32'd0;
16 -instr_mem[7] = 32'b00000000000000000110000000010000; // mfhi $12
17 -instr_mem[8] = 32'b00000000000000000110100000010010; // mflo $13
18 -instr_mem[9] = 32'b10101100000011010000000000111100; // sw $0 $13 60
19 -instr_mem[10] = 32'd0;
20 -instr_mem[11] = 32'b00010001000010110000000000000001; // beq $8 $11 +1
21 -instr_mem[12] = 32'b10001100000000010000000000111100; // lw $0 $1 60
22 -instr_mem[13] = 32'd0;
23 -instr_mem[14] = 32'b00000000000000000000000000001000; // jr $0
24 -
25 -
26 -
27 -end
28 -
29 -always @ (*) begin
30 - instruction = instr_mem[address/4];
31 -end
32 -
33 -endmodule
1 -D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
2 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
3 --- Compiling module ShiftLeft2
4 -
5 -Top level modules:
6 - ShiftLeft2
7 -
8 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
9 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
10 --- Compiling module InstructionMemory
11 -
12 -Top level modules:
13 - InstructionMemory
14 -
15 -} {} {}} {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v} {1 {vlog -work work -stats=none {D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Data Memory.v}
16 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
17 --- Compiling module DataMemory
18 -
19 -Top level modules:
20 - DataMemory
21 -
22 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
23 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
24 --- Compiling module testbench
25 -
26 -Top level modules:
27 - testbench
28 -
29 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/clock.v
30 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
31 --- Compiling module Clock
32 -
33 -Top level modules:
34 - Clock
35 -
36 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Adder.v
37 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
38 --- Compiling module Adder
39 -
40 -Top level modules:
41 - Adder
42 -
43 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
44 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
45 --- Compiling module SignExtend
46 -
47 -Top level modules:
48 - SignExtend
49 -
50 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
51 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
52 --- Compiling module Register
53 -
54 -Top level modules:
55 - Register
56 -
57 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Control.v
58 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
59 --- Compiling module Control
60 -
61 -Top level modules:
62 - Control
63 -
64 -} {} {}} D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v {1 {vlog -work work -stats=none D:/class/Capstone1/KNW_Project2/Project/SingleCycle/ALU.v
65 -Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015
66 --- Compiling module ALU
67 -
68 -Top level modules:
69 - ALU
70 -
71 -} {} {}}
1 -module test;
2 -
3 -reg[31:0] in1, in2;
4 -reg[3:0] ctrl;
5 -wire[31:0] out;
6 -wire a;
7 -
8 -ALU alu(in1, in2, ctrl, out, a);
9 -
10 -initial begin
11 - in1 = 32'd128;
12 - in2 = 32'd982;
13 - ctrl = 4'b1000;
14 - #100;
15 - in1 = 32'd123;
16 - in2 = 32'd246;
17 - ctrl = 4'b0010;
18 - #100;
19 - ctrl = 4'b1010;
20 - #100;
21 - ctrl = 4'b1011;
22 - #100;
23 -end
24 -
25 -/*
26 -wire clk;
27 -
28 -Clock clock(clk);
29 -*/
30 -
31 -/*
32 -reg[31:0] address, wdata;
33 -reg mr, mw;
34 -wire[31:0] rdata;
35 -
36 -DataMemory damem(address, wdata, mr, mw, rdata);
37 -
38 -initial begin
39 - address = 32'd0;
40 - wdata = 32'd127;
41 - mr = 1'b0;
42 - mw = 1'b1;
43 - #100;
44 - address = 32'd48;
45 - wdata = 32'd255;
46 - mr = 1'b0;
47 - mw = 1'b1;
48 - #100;
49 - address = 32'd48;
50 - wdata = 32'd255;
51 - mr = 1'b1;
52 - mw = 1'b0;
53 - #100;
54 - address = 32'd48;
55 - wdata = 32'd4;
56 - mr = 1'b0;
57 - mw = 1'b1;
58 - #100;
59 -end
60 -*/
61 -
62 -/*
63 -wire[31:0] regout1, regout2;
64 -reg[4:0] ins1, ins2, ins3;
65 -wire[31:0] aluresult;
66 -reg[3:0] aluctrl;
67 -reg rwrite;
68 -reg[31:0] aluin2;
69 -
70 -Register Regi(ins1, ins2, ins3, aluresult, rwrite, regout1, regout2);
71 -ALU alu(regout1, aluin2, aluctrl, aluresult);
72 -
73 -initial begin
74 - rwrite = 1;
75 - ins1 = 5'd0;
76 - ins2 = 5'd29;
77 - ins3 = 5'd7;
78 - aluin2 = 32'h7fffffff;
79 - aluctrl = 4'b0010;
80 - #100;
81 - rwrite = 1;
82 - ins1 = 5'd7;
83 - ins2 = 5'd7;
84 - ins3 = 5'd8;
85 - aluctrl = 4'b0010;
86 - #100;
87 - rwrite = 0;
88 - #100;
89 - rwrite = 1;
90 - ins1 = 5'd0;
91 - ins2 = 5'd29;
92 - ins3 = 5'd7;
93 - aluin2 = 32'h7fffffff;
94 - aluctrl = 4'b0010;
95 - #100;
96 - rwrite = 1;
97 - ins1 = 5'd7;
98 - ins2 = 5'd7;
99 - ins3 = 5'd8;
100 - aluctrl = 4'b0010;
101 - #100;
102 -end
103 -*/
104 -
105 -/*
106 -reg[31:0] input1, input2;
107 -reg[3:0] ctrl;
108 -wire[31:0] output1;
109 -wire zero;
110 -
111 -ALU testalu(input1, input2, ctrl, output1, zero);
112 -
113 -initial begin
114 - input1 <= 32'h0000000f;
115 - input2 <= 32'h000000f0;
116 - ctrl <= 4'h0; // add
117 - #100;
118 - ctrl <= 4'h1; // or
119 - #100;
120 - ctrl <= 4'h2; // add
121 - #100;
122 - ctrl <= 4'h6; // sub
123 - #100;
124 - ctrl <= 4'h7; // slt
125 - #100;
126 - ctrl <= 4'hc; // nor
127 - #100;
128 - input1 <= 32'h000000f0;
129 - input2 <= 32'h0000000f;
130 - ctrl <= 4'h6; // sub
131 - #100;
132 - input1 <= 32'h000000f0;
133 - input2 <= 32'h0000000f;
134 - ctrl <= 4'h6; // sub
135 - #100;
136 - input1 <= 32'h000000f0;
137 - input2 <= 32'h0000000f;
138 - ctrl <= 4'h6; // sub
139 - #100;
140 - input1 <= 32'h000000f0;
141 - input2 <= 32'h0000000f;
142 - ctrl <= 4'h6; // sub
143 - #100;
144 -end
145 -*/
146 -
147 -/*
148 -reg[31:0] input1;
149 -wire[31:0] output1;
150 -
151 -InstructionMemory im(input1, output1);
152 -
153 -initial
154 -begin
155 - input1 = {{28{1'b0}}, 4'b0000};
156 - #100;
157 - input1 = {{28{1'b0}}, 4'b1100};
158 - #100;
159 - input1 = {{28{1'b0}}, 4'b1000};
160 - #100;
161 - input1 = {{28{1'b0}}, 4'b0100};
162 - #100;
163 - input1 = {{28{1'b0}}, 4'b0000};
164 - #100;
165 -end
166 -*/
167 -
168 -/*
169 -reg[7:0] input1;
170 -wire[7:0] output1;
171 -
172 -Adder adder1(input1, 8'b00000001, output1);
173 -
174 -initial
175 -begin
176 - input1 = 8'b00001111;
177 - #100;
178 - input1 = 8'b00001000;
179 - #100;
180 - input1 = 8'b00000000;
181 - #100;
182 - input1 = 8'b11111111;
183 - #100;
184 -end
185 -*/
186 -endmodule
1 -m255
2 -K4
3 -z2
4 -13
5 -!s112 1.1
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8 -!i10f 100
9 -cModel Technology
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152 -FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/InstructionMemory.v
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161 -!s101 -O0
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169 -InTEk>^`Yjc4Xl2[WnZ3^Y3
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171 -R2
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173 -Z13 8D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
174 -Z14 FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v
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182 -Z16 !s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Mux.v|
183 -!s101 -O0
184 -!i113 1
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186 -n@mux32bit
187 -vMux5bit
188 -R6
189 -!i10b 1
190 -!s100 1oCn>`bHoZ=?A6[JF911T3
191 -I]EmV`Adl6kHglkN9IK>LX2
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208 -n@mux5bit
209 -vRegister
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211 -!i10b 1
212 -!s100 Bdb0dL`fj[<g;4lO0DTA?2
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218 -FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v
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220 -R3
221 -r1
222 -!s85 0
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224 -R11
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226 -!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/Register.v|
227 -!s101 -O0
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240 -FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/ShiftLeft2.v
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262 -FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/SignExtend.v
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265 -r1
266 -!s85 0
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271 -!s101 -O0
272 -!i113 1
273 -R5
274 -n@sign@extend
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276 -!s110 1590134078
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278 -!s100 Sm5D9nHWJl4JV?TA`lU4`0
279 -IW:K2A@A@^WBUal;dbVMEN0
280 -R1
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282 -w1589610276
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284 -FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v
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286 -R3
287 -r1
288 -!s85 0
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292 -!s90 -reportprogress|300|-work|work|-stats=none|D:/class/Capstone1/KNW_Project2/Project/SingleCycle/test.v|
293 -!s101 -O0
294 -!i113 1
295 -R5
296 -vtestbench
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305 -FD:/class/Capstone1/KNW_Project2/Project/SingleCycle/testbench.v
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314 -!s101 -O0
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316 -R5
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